✓ CI.checkpatch: success for PSR DSB support (rev3)

[Patchwork]

== Series Details ==

Series: PSR DSB support (rev3)
URL   : https://patchwork.freedesktop.org/series/142521/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8ea80b3c4e78f54b8b0cefda7b1006be9494bbab
Author: Jouni Högander <jouni.hogander at intel.com>
Date:   Thu Jan 9 09:31:37 2025 +0200

    drm/i915/psr: Allow DSB usage when PSR is enabled
    
    Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
    usage also when PSR is enabled for LunarLake onwards.
    
    Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
+ /mt/dim checkpatch 9e5828f71dbb3bf6dff6a2bcfaa761d048344b2a drm-intel
0aefabab4e01 drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update
9990bd412593 drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update
aff8095b56d2 drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update
79d4aee6aef8 drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers
a61928354a23 drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards
7c8ed354d33a drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB
f43876337c0e drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use
c8a6baeaa89e drm/i915/psr: Add intel_psr_is_psr_mode_changing
e3a566cd1159 drm/i915/display: Don't use DSB if psr mode changing
8ea80b3c4e78 drm/i915/psr: Allow DSB usage when PSR is enabled