[PATCH 5/5] drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Ankit
> Nautiyal
> Sent: Tuesday, August 13, 2024 8:50 AM
> To: intel-gfx at lists.freedesktop.org; intel-xe at lists.freedesktop.org
> Cc: jani.nikula at linux.intel.com
> Subject: [PATCH 5/5] drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY
> 
> Try HDMI PLL alogorithm for C10 PHY, if there are no pre-computed tables.
> Also get rid of the helpers to get rate for HDMI for C10/20 PHY, as we no
> longer depend only on pre-computed tables.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal at intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 49 +++++---------------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h |  1 -
>  drivers/gpu/drm/i915/display/intel_hdmi.c    | 10 ----
>  3 files changed, 11 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 4a6c3040ca15..2fee6baaa2ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -16,6 +16,7 @@
>  #include "intel_hdmi.h"
>  #include "intel_panel.h"
>  #include "intel_psr.h"
> +#include "intel_snps_hdmi_pll.h"
>  #include "intel_tc.h"
> 
>  #define MB_WRITE_COMMITTED      true
> @@ -1970,19 +1971,6 @@ static const struct intel_c20pll_state * const
> mtl_c20_hdmi_tables[] = {
>  	NULL,
>  };
> 
> -static int intel_c10_phy_check_hdmi_link_rate(int clock) -{
> -	const struct intel_c10pll_state * const *tables = mtl_c10_hdmi_tables;
> -	int i;
> -
> -	for (i = 0; tables[i]; i++) {
> -		if (clock == tables[i]->clock)
> -			return MODE_OK;
> -	}
> -
> -	return MODE_CLOCK_RANGE;
> -}
> -
>  static const struct intel_c10pll_state * const *  intel_c10pll_tables_get(struct
> intel_crtc_state *crtc_state,
>  			struct intel_encoder *encoder)
> @@ -2044,6 +2032,16 @@ static int intel_c10pll_calc_state(struct
> intel_crtc_state *crtc_state,
>  		}
>  	}
> 
> +	/* For HDMI PLLs try SNPS PHY algorithm, if there are no precomputed
> tables */
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
> +		intel_snps_hdmi_pll_compute_c10pll(&crtc_state-
> >dpll_hw_state.cx0pll.c10,
> +						   crtc_state->port_clock);
> +		intel_c10pll_update_pll(crtc_state, encoder);
> +		crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
> +
> +		return 0;
> +	}
> +
>  	return -EINVAL;
>  }
> 
> @@ -2210,31 +2208,6 @@ static int intel_c20_compute_hdmi_tmds_pll(u64
> pixel_clock, struct intel_c20pll_
>  	return 0;
>  }
> 
> -static int intel_c20_phy_check_hdmi_link_rate(int clock) -{
> -	const struct intel_c20pll_state * const *tables = mtl_c20_hdmi_tables;
> -	int i;
> -
> -	for (i = 0; tables[i]; i++) {
> -		if (clock == tables[i]->clock)
> -			return MODE_OK;
> -	}
> -
> -	if (clock >= 25175 && clock <= 594000)
> -		return MODE_OK;
> -
> -	return MODE_CLOCK_RANGE;
> -}
> -
> -int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock) -{
> -	struct intel_digital_port *dig_port = hdmi_to_dig_port(hdmi);
> -
> -	if (intel_encoder_is_c10phy(&dig_port->base))
> -		return intel_c10_phy_check_hdmi_link_rate(clock);
> -	return intel_c20_phy_check_hdmi_link_rate(clock);
> -}
> -
>  static const struct intel_c20pll_state * const *  intel_c20_pll_tables_get(struct
> intel_crtc_state *crtc_state,
>  			 struct intel_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9004b99bb51f..2e3076261d30 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -43,7 +43,6 @@ bool intel_cx0pll_compare_hw_state(const struct
> intel_cx0pll_state *a,
>  				   const struct intel_cx0pll_state *b);  void
> intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
>  				     const struct intel_crtc_state *crtc_state); -
> int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
> int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
> 
>  #endif /* __INTEL_CX0_PHY_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
> b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index bed54a3588d9..4706adf54dfa 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -1878,16 +1878,6 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi,
>  	if (intel_encoder_is_tc(encoder) && clock > 500000 && clock <
> 532800)
>  		return MODE_CLOCK_RANGE;
> 
> -	/*
> -	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
> -	 * set of link rates.
> -	 *
> -	 * FIXME: We will hopefully get an algorithmic way of programming
> -	 * the MPLLB for HDMI in the future.
> -	 */
> -	if (DISPLAY_VER(dev_priv) >= 14)
> -		return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
> -
>  	return MODE_OK;
>  }
> 
> --
> 2.45.2