✓ CI.checkpatch: success for series starting with [1/2] drm/xe: Introduce GuC PC debugfs

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/xe: Introduce GuC PC debugfs
URL   : https://patchwork.freedesktop.org/series/143533/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8d923d24265f196d0a37aaa06bb6bac8830d152c
Author: Rodrigo Vivi <rodrigo.vivi at intel.com>
Date:   Tue Jan 14 18:24:43 2025 -0500

    drm/xe/lnl: Enable GuC SLPC DCC task
    
    Enable DCC (Duty Cycle Control) in Lunar Lake.
    
    DCC is the SLPC task that tries to keep
    the GT from operating inefficiently when thermally constrained.
    
    Although the recommendation is to enable it, LNL GuC is leaving
    it disabled by default on LNL.
    
    It would minimize the GT frequency oscillation on throttled
    scenarios, which could potentially reduce latencies.
    
    v2: Move set_policies call after wait for running state, so
        we ensure it is not overwritten. (Vinay)
    v3: Fix English in the commit message (Jonathan)
    v4: Also set disable to 0 so DCC can really get into effect.
    
    Cc: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
    Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com> #v3
    Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
    Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar at intel.com>
+ /mt/dim checkpatch a45139b1e7578c7a4f1cbe8fae0943416a174136 drm-intel
39e753013d95 drm/xe: Introduce GuC PC debugfs
8d923d24265f drm/xe/lnl: Enable GuC SLPC DCC task