✓ CI.checkpatch: success for drm/i915/display: HDMI C10 PLL entry for 265250 MHz

[Patchwork]

== Series Details ==

Series: drm/i915/display: HDMI C10 PLL entry for 265250 MHz
URL   : https://patchwork.freedesktop.org/series/143576/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit ed77923ca98e7eaf94a1ce6c4623b2657ba0ca06
Author: Clint Taylor <clinton.a.taylor at intel.com>
Date:   Wed Jan 15 15:08:59 2025 -0800

    drm/i915/display: HDMI C10 PLL entry for 265250 MHz
    
    Add PLL values for 265.250MHz pixel clock to support recent 3440x1440
    monitors.
    
    Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
+ /mt/dim checkpatch 83dd30e2ec24ab8307774b149fcd998a4191eec2 drm-intel
ed77923ca98e drm/i915/display: HDMI C10 PLL entry for 265250 MHz