[PATCH 2/2] drm/xe: Refactor max_remote_tiles

[Matt Roper]

On Thu, Jan 16, 2025 at 11:16:26AM -0800, Summers, Stuart wrote:
> On Thu, 2025-01-16 at 18:24 +0530, Sai Teja Pottumuttu wrote:
> > max_remote_tiles is more related to the platform than the GT IP. Thus
> > move it to platform descriptor from graphics descriptor. Note that
> > the
> > FIXME is no more required, thus it can be dropped.
> 
> I think we still want this FIXME. Has anything fundamentally changed in
> the driver wrt tiles vs gts?

I think at this point we've fixed most of the code to use
xe->info.gt_count in the proper places instead of xe->info.tile_count.
E.g., commit 37efea9ca258 ("drm/xe: Allow GT looping and lookup on
standalone media") and similar changes.  If there are places still
incorrectly using tile_count then we should fix those, but I'm not aware
of any off the top of my head.

The thing that is still a bit of an open issue is if we eventually have
a platform that has both multiple tiles _and_ multiple GTs per tile,
we'll need to figure out how we want to number the GTs (for example,
0=p 1=m 2=p 3=m vs 0=p 1=p 2=m 3=m) and then rework code like
xe_device_get_gt() to use that.  But that decision can wait until we
actually have such a platform.


Matt

> 
> Thanks,
> Stuart
> 
> > 
> > Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu at intel.com>
> > ---
> >  drivers/gpu/drm/xe/xe_pci.c       | 9 +++------
> >  drivers/gpu/drm/xe/xe_pci_types.h | 2 --
> >  2 files changed, 3 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > b/drivers/gpu/drm/xe/xe_pci.c
> > index f59c1acae23f..7f17e5ea6edd 100644
> > --- a/drivers/gpu/drm/xe/xe_pci.c
> > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > @@ -55,6 +55,7 @@ struct xe_device_desc {
> >         enum xe_platform platform;
> >  
> >         u8 dma_mask_size;
> > +       u8 max_remote_tiles:2;
> >  
> >         u8 require_force_probe:1;
> >         u8 is_dgfx:1;
> > @@ -136,7 +137,6 @@ static const struct xe_graphics_desc
> > graphics_xehpc = {
> >                 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
> >  
> >         XE_HP_FEATURES,
> > -       .max_remote_tiles = 1,
> >         .va_bits = 57,
> >         .vm_max_level = 4,
> >         .vram_flags = XE_VRAM_FLAGS_NEED64K,
> > @@ -329,6 +329,7 @@ static const __maybe_unused struct xe_device_desc
> > pvc_desc = {
> >         .dma_mask_size = 52,
> >         .has_display = false,
> >         .has_heci_gscfi = 1,
> > +       .max_remote_tiles = 1,
> >         .require_force_probe = true,
> >  };
> >  
> > @@ -635,6 +636,7 @@ static int xe_info_init_early(struct xe_device
> > *xe,
> >         xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
> >                                  xe_modparam.probe_display &&
> >                                  desc->has_display;
> > +       xe->info.tile_count = 1 + desc->max_remote_tiles;
> >  
> >         err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);
> >         if (err)
> > @@ -706,12 +708,7 @@ static int xe_info_init(struct xe_device *xe,
> >          * version 13 or higher has an additional dedicated media
> > GT.  And
> >          * depending on the graphics IP there may be additional
> > "remote tiles."
> >          * All of these together determine the overall GT count.
> > -        *
> > -        * FIXME: 'tile_count' here is misnamed since the rest of the
> > driver
> > -        * treats it as the number of GTs rather than just the number
> > of tiles.
> >          */
> > -       xe->info.tile_count = 1 + graphics_desc->max_remote_tiles;
> > -
> >         for_each_remote_tile(tile, xe, id) {
> >                 int err;
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_pci_types.h
> > b/drivers/gpu/drm/xe/xe_pci_types.h
> > index 7437415a54d5..b96423844952 100644
> > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > @@ -19,8 +19,6 @@ struct xe_graphics_desc {
> >  
> >         u64 hw_engine_mask;     /* hardware engines provided by
> > graphics IP */
> >  
> > -       u8 max_remote_tiles:2;
> > -
> >         u8 has_asid:1;
> >         u8 has_atomic_enable_pte_bit:1;
> >         u8 has_flat_ccs:1;
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation