[PATCH v3 1/2] drm/xe/xe: Add Wa_16021333562 and Wa_14016712196

[Upadhyay, Tejas]

> -----Original Message-----
> From: Bhatia, Aradhya <aradhya.bhatia at intel.com>
> Sent: Monday, January 20, 2025 11:39 AM
> To: Roper, Matthew D <matthew.d.roper at intel.com>
> Cc: Intel XE List <intel-xe at lists.freedesktop.org>; De Marchi, Lucas
> <lucas.demarchi at intel.com>; Upadhyay, Tejas <tejas.upadhyay at intel.com>;
> Ghimiray, Himal Prasad <himal.prasad.ghimiray at intel.com>; Siddiqui, Ayaz A
> <ayaz.siddiqui at intel.com>; Bhatia, Aradhya <aradhya.bhatia at intel.com>
> Subject: [PATCH v3 1/2] drm/xe/xe: Add Wa_16021333562 and
> Wa_14016712196
> 
> Wa_16021333562 and Wa_14016712196 are permanent workarounds that
> apply to multiple platforms. Wa_16021333562 applies to platforms ranging
> from TGL (12.00) to Xe_LPM (13.00), while Wa_14016712196 from DG2
> (12.55) to Xe_LPG (12.74).
> 
> Signed-off-by: Aradhya Bhatia <aradhya.bhatia at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_guc_ads.c    | 5 +++++
>  drivers/gpu/drm/xe/xe_ring_ops.c   | 3 +++
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 4 ++++
>  3 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c
> b/drivers/gpu/drm/xe/xe_guc_ads.c index fab259adc380..8ef044ddd682
> 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -376,6 +376,11 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
> 
> 	GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET,
>  					&offset, &remain);
> 
> +	if (XE_WA(gt, 16021333562))

You can OR with existing check!, like if (XE_WA(gt, 14019882105) || XE_WA(gt, 16021333562)) . Also there was firmware check, although xe might not be using that firmware version, so should be ok.	

> +		guc_waklv_enable_simple(ads,
> +
> 	GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOC
> KED,
> +					&offset, &remain);
> +
>  	size = guc_ads_waklv_size(ads) - remain;
>  	if (!size)
>  		return;
> diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c
> b/drivers/gpu/drm/xe/xe_ring_ops.c
> index 9f327f27c072..22c226c30df9 100644
> --- a/drivers/gpu/drm/xe/xe_ring_ops.c
> +++ b/drivers/gpu/drm/xe/xe_ring_ops.c
> @@ -192,6 +192,9 @@ static int emit_render_cache_flush(struct
> xe_sched_job *job, u32 *dw, int i)
>  	else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
>  		flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> 
> +	if (XE_WA(gt, 14016712196))
> +		i = emit_pipe_control(dw, i, 0,
> PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0,
> +0);

I think offset you need to pass is LRC_PPHWSP_SCRATCH_ADDR

Tejas
> +
>  	return emit_pipe_control(dw, i,
> PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);  }
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules
> b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 40438c3d9b72..d7f7d617d490 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -42,3 +42,7 @@
>  no_media_l3	MEDIA_VERSION(3000)
>  14022866841	GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
>  		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
> +16021333562	GRAPHICS_VERSION_RANGE(1200, 1274)
> +		MEDIA_VERSION(1300)
> +14016712196	GRAPHICS_VERSION(1255)
> +		GRAPHICS_VERSION_RANGE(1270, 1274)
> --
> 2.34.1