[PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY

[Almahallawy, Khaled]

Thank You for the series. 
Tested a modeline that is not pre-computed and able to see pixel clock
calculation done correctly and the analyzer turns on:

adjusted mode: "3440x1440": 50 265250 3440 3488 3520 3600 1440 1443
1453 1474 0x48 0x9
crtc timings: clock=265250, hd=3440 hb=3440-3600 hs=3488-3520 ht=3600,
vd=1440 vb=1440-1474 vs=1443-1453 vt=1474, flags=0x9

Tested-by: Khaled Almahallawy <khaled.almahallawy at intel.com>

On Mon, 2025-01-20 at 09:51 +0530, Ankit Nautiyal wrote:
> The HDMI PLL programming involves pre-calculated values for specific
> frequencies and an algorithm to compute values for other frequencies.
> While the algorithm itself wasn't part of the driver, tables were
> added based on it for known modes.
> 
> Some HDMI modes were pruned due to lack of support (for example
> issues
> [1],[2], and [3]).
> This series adds the algorithm for computing HDMI PLLs for
> SNPS/C10PHY
> to work with all modes supported by the hardware.
> 
> The original algorithm uses floating-point math, which has been
> converted to integers while preserving precision. As a result,
> the values in the existing computable tables are very close but not
> exact. Testing with DG2 and MTL on various panels revealed no issues.
> 
> [1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722
> [2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654
> [3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956
> 
> Rev2:
> -Change the name of the new file for HDMI PLL algorithm.
> -Fix styling issues and bit refactoring for readbility.
> -Fix issues reported by kernel test bot.
> 
> Rev3:
> -Modify the names of helper functions to align with filename.
> 
> Rev4:
> -Rebase, added Bspec references, and address review comments.
> 
> Ankit Nautiyal (5):
>   drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for
> DG2
>   drm/i915/snps_phy: Use HDMI PLL algorithm for DG2
>   drm/i915/cx0_phy_regs: Add C10 registers bits
>   drm/i915/intel_snps_hdmi_pll: Compute C10 HDMI PLLs with algorithm
>   drm/i915/cx0_phy: Use HDMI PLL algorithm for C10 PHY
> 
>  drivers/gpu/drm/i915/Makefile                 |   1 +
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  49 +--
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |   1 -
>  .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  24 ++
>  drivers/gpu/drm/i915/display/intel_hdmi.c     |  12 -
>  .../drm/i915/display/intel_snps_hdmi_pll.c    | 364
> ++++++++++++++++++
>  .../drm/i915/display/intel_snps_hdmi_pll.h    |  17 +
>  drivers/gpu/drm/i915/display/intel_snps_phy.c |  37 +-
>  drivers/gpu/drm/i915/display/intel_snps_phy.h |   1 -
>  drivers/gpu/drm/xe/Makefile                   |   1 +
>  10 files changed, 427 insertions(+), 80 deletions(-)
>  create mode 100644
> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.c
>  create mode 100644
> drivers/gpu/drm/i915/display/intel_snps_hdmi_pll.h
>