[PATCH] drm/i915/cx0: Set ssc_enabled for c20 too

[Nautiyal, Ankit K]

On 1/22/2025 11:00 AM, Suraj Kandpal wrote:
> ssc_enabled does not get set for c20 phy.
> This patch makes sure we set ssc_enabled for both c10 and c20.
Remove 'patch'.
Add Bspec: 74491
> Signed-off-by: Suraj Kandpal <suraj.kandpal at intel.com>

LGTM. With suggested changes, this is:

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_cx0_phy.c | 14 +++++++++++---
>   1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 058013c74991..d123851e53cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2033,21 +2033,27 @@ intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
>   	return NULL;
>   }
>   
> -static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
> +static void intel_cx0pll_update_ssc(struct intel_crtc_state *crtc_state,
>   				    struct intel_encoder *encoder)
>   {
>   	struct intel_display *display = to_intel_display(encoder);
>   	struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
> -	int i;
>   
>   	if (intel_crtc_has_dp_encoder(crtc_state)) {
>   		if (intel_panel_use_ssc(display)) {
>   			struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> -
>   			pll_state->ssc_enabled =
>   				(intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5);
>   		}
>   	}
> +}
> +
> +static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
> +				    struct intel_encoder *encoder)
> +{
> +	struct intel_display *display = to_intel_display(encoder);
> +	struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
> +	int i;
>   
>   	if (pll_state->ssc_enabled)
>   		return;
> @@ -2070,6 +2076,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state,
>   	for (i = 0; tables[i]; i++) {
>   		if (crtc_state->port_clock == tables[i]->clock) {
>   			crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i];
> +			intel_cx0pll_update_ssc(crtc_state, encoder);
>   			intel_c10pll_update_pll(crtc_state, encoder);
>   			crtc_state->dpll_hw_state.cx0pll.use_c10 = true;
>   
> @@ -2354,6 +2361,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state,
>   	for (i = 0; tables[i]; i++) {
>   		if (crtc_state->port_clock == tables[i]->clock) {
>   			crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i];
> +			intel_cx0pll_update_ssc(crtc_state, encoder);
>   			crtc_state->dpll_hw_state.cx0pll.use_c10 = false;
>   			return 0;
>   		}