[PATCH 35/35] drm/i915/display: Use VRR timings for MTL+ in modeset sequence

[Ankit Nautiyal]

While enabling pipe currently we use the non vrr timings first and then
enable the VRR timings later.
>From MTL+ we will always have VRR timing generarator in use, so start
the transcoder in vrr mode.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++--
 drivers/gpu/drm/i915/display/intel_vblank.c  |  8 +++++---
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6d01c76d17ae..affdcc4be5f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7179,6 +7179,7 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 			      struct intel_crtc *crtc)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_display *display = to_intel_display(state);
 	const struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_crtc *pipe_crtc;
@@ -7191,8 +7192,16 @@ static void intel_enable_crtc(struct intel_atomic_state *state,
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
 
-		/* VRR will be enable later, if required */
-		intel_crtc_update_active_timings(pipe_crtc_state, false);
+		/*
+		 * For MTL+ we are always using VRR TG.
+		 * For previous platforms VRR will be enable later, if required
+		 */
+		if (intel_vrr_always_use_vrr_tg(display))
+			intel_crtc_update_active_timings(pipe_crtc_state,
+							 intel_vrrtg_is_enabled(pipe_crtc_state));
+		else
+			intel_crtc_update_active_timings(pipe_crtc_state, false);
+
 	}
 
 	dev_priv->display.funcs.display->crtc_enable(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 4efd4f7d497a..0c3d07f30b92 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -661,9 +661,11 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 	adjusted_mode = &crtc_state->hw.adjusted_mode;
 
 	if (crtc->mode_flags & I915_MODE_FLAG_VRR) {
-		/* timing changes should happen with VRR disabled */
-		drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
-			    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
+		/* Prior to MTL+, timing changes should happen with VRR disabled */
+		if (!intel_vrr_always_use_vrr_tg(display)) {
+			drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) ||
+				    new_crtc_state->update_m_n || new_crtc_state->update_lrr);
+		}
 
 		if (intel_vrr_is_push_sent(crtc_state))
 			evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
-- 
2.45.2