✓ CI.checkpatch: success for PSR DSB support (rev6)

[Patchwork]

== Series Details ==

Series: PSR DSB support (rev6)
URL   : https://patchwork.freedesktop.org/series/142521/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit fda1e78de8d32f16c15c805066b880c13cc64ed9
Author: Jouni Högander <jouni.hogander at intel.com>
Date:   Mon Jan 27 12:28:46 2025 +0200

    drm/i915/psr: Allow DSB usage when PSR is enabled
    
    Now as we have correct PSR2_MAN_TRK_CTL handling in place we can allow DSB
    usage also when PSR is enabled for LunarLake onwards.
    
    Signed-off-by: Jouni Högander <jouni.hogander at intel.com>
    Reviewed-by: Animesh Manna <animesh.manna at intel.com>
+ /mt/dim checkpatch 006a892140827b356eb4ad5a5e9b947477791ba8 drm-intel
3a54bfa96285 drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update
d060fa1ac79d drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update
22c64d278c75 drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update
ecf669f4eaa9 drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers
77ea9c76cea3 drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards
46814c8ea397 drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB
94e7a4d3871e drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use
a978f2c78b77 drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit
ea3a09c4e639 drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled
6832b35b8ddb drm/i915/psr: Add function for triggering "Frame Change" event
2bce779c4415 drm/i915/display: Ensure we have "Frame Change" event in DSB commit
fda1e78de8d3 drm/i915/psr: Allow DSB usage when PSR is enabled