✗ CI.checkpatch: warning for drm/i915/xe3: FBC Dirty rect feature support (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/xe3: FBC Dirty rect feature support (rev6)
URL   : https://patchwork.freedesktop.org/series/141526/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b6d31f794d558bb28ad7d4f11448bf4d3d8bb152
Author: Vinod Govindapillai <vinod.govindapillai at intel.com>
Date:   Tue Jan 28 17:54:18 2025 +0200

    drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled
    
    It is not recommended to have both FBC dirty rect and PSR2
    selective fetch be enabled at the same time. If PSR2 selective
    fetch or panel replay is on, mark FBC as not possible.
    
    v2: fix the condition to disable FBC if PSR2 enabled (Jani)
    
    v3: use HAS_FBC_DIRTY_RECT()
    
    Bspec: 68881
    Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
+ /mt/dim checkpatch 20759526c04a7f776f477bee66300dae33b51872 drm-intel
911318d9032e drm/i915/xe3: add register definitions for fbc dirty rect support
-:24: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:107:
+#define   FBC_DIRTY_RECT_START_LINE(val)	REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))

total: 0 errors, 1 warnings, 0 checks, 15 lines checked
f29ae72ad1da drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect support
1721f06a5e02 drm/i915/display: get old_plane_state to the check_plane routine
3e5fbb905e3c drm/i915/display: update and store the plane damage clips
0e341dc2cbba drm/i915/xe3: avoid calling fbc activate if fbc is active
e6e9f265ebff drm/i915/xe3: dirty rect support for FBC
b6d31f794d55 drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled