[PATCH 01/17] drm/i915/dsi: Use TRANS_DDI_FUNC_CTL's own port width macro

[Jani Nikula]

On Wed, 29 Jan 2025, Imre Deak <imre.deak at intel.com> wrote:
> The format of the port width field in the DDI_BUF_CTL and the
> TRANS_DDI_FUNC_CTL registers are different starting with MTL, where the
> x3 lane mode for HDMI FRL has a different encoding in the two registers.
> To account for this use the TRANS_DDI_FUNC_CTL's own port width macro.
>
> Signed-off-by: Imre Deak <imre.deak at intel.com>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ee1c3fb500a73..11bfb357508b7 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -809,8 +809,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>  		/* select data lane width */
>  		tmp = intel_de_read(display,
>  				    TRANS_DDI_FUNC_CTL(display, dsi_trans));
> -		tmp &= ~DDI_PORT_WIDTH_MASK;
> -		tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
> +		tmp &= ~TRANS_DDI_PORT_WIDTH_MASK;
> +		tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count);
>  
>  		/* select input pipe */
>  		tmp &= ~TRANS_DDI_EDP_INPUT_MASK;

-- 
Jani Nikula, Intel