[PATCH 3/5] drm/xe/gen12: L3 recommended hashing mask

[Lucas De Marchi]

On Thu, Jan 30, 2025 at 08:23:34AM -0800, Matt Roper wrote:
>On Wed, Jan 29, 2025 at 12:30:28PM -0600, Lucas De Marchi wrote:
>> On Wed, Jan 29, 2025 at 03:56:25PM +0000, Tvrtko Ursulin wrote:
>> > According to the i915 codebase xe missed to set the recommended
>> > performance tuning for L3 hashing which is applicable to all legacy Gen12
>> > platforms. Lets add it.
>> >
>> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at igalia.com>
>> > References: c46c5fb725be ("drm/i915/gen12: Apply recommended L3 hashing mask")
>> > Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>> > Cc: Matt Roper <matthew.d.roper at intel.com>
>> > ---
>> > I could not find the reference to this in the public docs, including
>> > confirmation whether 0xb004 even exists on for example TGL. Then for ADL I
>> > don't see that PRMs have been made public at all.
>>
>> leaving this part to confirm later. Matt Roper may remember better and
>> chime in.
>
>The tuning setting here is still documented for Xe_LP and Xe_LP+
>platforms on bspec page 31870, so this seems legitimate.  I think the
>only reason we never added it to this driver was because Xe's support
>for the pre-Xe2 platforms was never intended for any real-world use,
>just for early driver development when Xe2 hardware still wasn't
>available.

thanks for confirming. Let's add the bspec number in the next rev.

>
>The register itself exists on the Xe_LP and Xe_LP+ platforms, even
>though it isn't included in the public PRMs for some reason.  It was
>removed in Xe_HP, and the tuning no longer applies after that.
>
>>
>> > ---
>> > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
>> > drivers/gpu/drm/xe/xe_tuning.c       | 6 ++++++
>> > 2 files changed, 9 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > index 096859072396..909638b18557 100644
>> > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> > @@ -366,6 +366,9 @@
>> > #define   XEHPC_OVRLSCCC			REG_BIT(0)
>> >
>> > /* L3 Cache Control */
>> > +#define GEN8_GARBCNTL                          XE_REG(0xb004)
>>
>> mind the commit 0bc519d20ffa ("drm/xe: Remove GEN[0-9]*_ prefixes")
>> GEN<x> prefixes/suffixes are not here on purpose.
>> When we refer to GEN12, it's XELP, or simply drop the prefix when it's
>> not needed.
>>
>> Registers here are sorted by address, so it should be before
>> XEHPC_LNCFMISCCFGREG0
>>
>>
>>
>> > +#define   GEN12_BUS_HASH_CTL_BIT_EXC           REG_BIT(7)
>> > +
>> > #define LNCFCMOCS_REG_COUNT			32
>> > #define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
>> > #define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
>> > diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
>> > index 9e7ec36dbd47..b21a59578ba3 100644
>> > --- a/drivers/gpu/drm/xe/xe_tuning.c
>> > +++ b/drivers/gpu/drm/xe/xe_tuning.c
>> > @@ -107,6 +107,12 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>> > 						FF_MODE2_TDS_TIMER_128))
>> > 	},
>> >
>> > +	{ XE_RTP_NAME("Tuning: L3 Hashing Mask"),
>> > +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1254),
>>
>> 50..55 are made up in sw... I believe it's safe at this point to just use
>> GRAPHICS_VERSION_RANGE(1200, 1250)
>
>Generally we apply rules to the specific range of platforms that they do
>apply to.  In this case the tuning applies to Xe_LP platforms (12.00 for
>TGL, RKL, and ADL-*) and Xe_LP+ (12.10 for DG1).  So I'd just write this
>range as (1200, 1210).  There aren't any platforms that use any
>subsequent version numbers until DG2's Xe_HP shows up at 12.55, so it
>doesn't really matter from a functional perspective, but I still think
>[1200, 1210] is more precise than [1200, 1250].

Ok, I was assuming the by using 1254 the intention was to cover 1250 and
exclude 1255 onward. If 1250 doesn't have that, then using 1210 should
be sufficient indeed. Bspec 68331 doesn't show it, so agreed.

Lucas De Marchi

>
>
>Matt
>
>>
>> Lucas De Marchi
>>
>> > +		       FUNC(xe_rtp_match_first_render_or_compute)),
>> > +	  XE_RTP_ACTIONS(CLR(GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC))
>> > +	},
>> > +
>> > 	/* DG2 */
>> >
>> > 	{ XE_RTP_NAME("Tuning: L3 cache"),
>> > --
>> > 2.48.0
>> >
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation