[PATCH v4 2/2] drm/xe/oa: Refactor WAs to use XE_WA() macro

[Lucas De Marchi]

On Thu, Jan 30, 2025 at 05:59:39AM +0000, Aradhya Bhatia wrote:
>Refactor Wa_18013179988, Wa_14015568240, Wa_1508761755, and
>Wa_1509372804, to use the proper workaround-check implementation for
>out-of-band workarounds, XE_WA(), and drop the use of the platform
>based WA selection.
>
>Reviewed-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
>Signed-off-by: Aradhya Bhatia <aradhya.bhatia at intel.com>
>---
> drivers/gpu/drm/xe/xe_oa.c         | 30 +++++++++---------------------
> drivers/gpu/drm/xe/xe_wa_oob.rules |  5 +++++
> 2 files changed, 14 insertions(+), 21 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
>index fa873f3d0a9d..5050bc7c7555 100644
>--- a/drivers/gpu/drm/xe/xe_oa.c
>+++ b/drivers/gpu/drm/xe/xe_oa.c
>@@ -12,6 +12,8 @@
> #include <drm/drm_managed.h>
> #include <uapi/drm/xe_drm.h>
>
>+#include <generated/xe_wa_oob.h>
>+
> #include "abi/guc_actions_slpc_abi.h"
> #include "instructions/xe_mi_commands.h"
> #include "regs/xe_engine_regs.h"
>@@ -35,6 +37,7 @@
> #include "xe_sched_job.h"
> #include "xe_sriov.h"
> #include "xe_sync.h"
>+#include "xe_wa.h"
>
> #define DEFAULT_POLL_FREQUENCY_HZ 200
> #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
>@@ -811,11 +814,8 @@ static void xe_oa_disable_metric_set(struct xe_oa_stream *stream)
> 	struct xe_mmio *mmio = &stream->gt->mmio;
> 	u32 sqcnt1;
>
>-	/*
>-	 * Wa_1508761755:xehpsdv, dg2
>-	 * Enable thread stall DOP gating and EU DOP gating.
>-	 */
>-	if (stream->oa->xe->info.platform == XE_DG2) {
>+	/* Enable thread stall DOP gating and EU DOP gating. */
>+	if (XE_WA(stream->gt, 1508761755)) {
> 		xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN,
> 					  _MASKED_BIT_DISABLE(STALL_DOP_GATING_DISABLE));
> 		xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2,
>@@ -1064,11 +1064,10 @@ static int xe_oa_enable_metric_set(struct xe_oa_stream *stream)
> 	int ret;
>
> 	/*
>-	 * Wa_1508761755:xehpsdv, dg2
> 	 * EU NOA signals behave incorrectly if EU clock gating is enabled.
> 	 * Disable thread stall DOP gating and EU DOP gating.
> 	 */
>-	if (stream->oa->xe->info.platform == XE_DG2) {
>+	if (XE_WA(stream->gt, 1508761755)) {
> 		xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN,
> 					  _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
> 		xe_gt_mcr_multicast_write(stream->gt, ROW_CHICKEN2,
>@@ -1719,12 +1718,10 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream,
> 	}
>
> 	/*
>-	 * Wa_1509372804:pvc
>-	 *
> 	 * GuC reset of engines causes OA to lose configuration
> 	 * state. Prevent this by overriding GUCRC mode.
> 	 */
>-	if (stream->oa->xe->info.platform == XE_PVC) {
>+	if (XE_WA(stream->gt, 1509372804)) {
> 		ret = xe_guc_pc_override_gucrc_mode(&gt->uc.guc.pc,
> 						    SLPC_GUCRC_MODE_GUCRC_NO_RC6);
> 		if (ret)
>@@ -1856,23 +1853,14 @@ u32 xe_oa_timestamp_frequency(struct xe_gt *gt)
> {
> 	u32 reg, shift;
>
>-	/*
>-	 * Wa_18013179988:dg2
>-	 * Wa_14015568240:pvc
>-	 * Wa_14015846243:mtl
>-	 */
>-	switch (gt_to_xe(gt)->info.platform) {
>-	case XE_DG2:
>-	case XE_PVC:
>-	case XE_METEORLAKE:
>+	if (XE_WA(gt, 18013179988) || XE_WA(gt, 14015568240)) {
> 		xe_pm_runtime_get(gt_to_xe(gt));
> 		reg = xe_mmio_read32(&gt->mmio, RPM_CONFIG0);
> 		xe_pm_runtime_put(gt_to_xe(gt));
>
> 		shift = REG_FIELD_GET(RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK, reg);
> 		return gt->info.reference_clock << (3 - shift);

one change in behavior here that is good to note: For MTL, previously
we'd do this to both GTs. Now this will only apply to the graphics gt,
and media GT will be skipped. According to the wa db, this is the
correct behavior, so lgtm. Ashutosh, is there any bug reported for OA in
mtl wrt timestamp frequency?

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>-
>-	default:
>+	} else {
> 		return gt->info.reference_clock;
> 	}
> }
>diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
>index ea72bcc02e1e..1dd02a231926 100644
>--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
>+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
>@@ -47,3 +47,8 @@ no_media_l3	MEDIA_VERSION(3000)
> 		MEDIA_VERSION(1300)
> 14016712196	GRAPHICS_VERSION(1255)
> 		GRAPHICS_VERSION_RANGE(1270, 1274)
>+14015568240	GRAPHICS_VERSION_RANGE(1255, 1260)
>+18013179988	GRAPHICS_VERSION(1255)
>+		GRAPHICS_VERSION_RANGE(1270, 1274)
>+1508761755	GRAPHICS_VERSION(1255)
>+		GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)
>-- 
>2.45.2
>