✗ CI.checkpatch: warning for drm/i915/xe3: FBC Dirty rect feature support (rev7)

[Patchwork]

== Series Details ==

Series: drm/i915/xe3: FBC Dirty rect feature support (rev7)
URL   : https://patchwork.freedesktop.org/series/141526/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 03cef2a3984585370a63859a6c77d0682b6e1dd9
Author: Vinod Govindapillai <vinod.govindapillai at intel.com>
Date:   Thu Jan 30 23:00:26 2025 +0200

    drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled
    
    It is not recommended to have both FBC dirty rect and PSR2
    selective fetch be enabled at the same time. If PSR2 selective
    fetch or panel replay is on, mark FBC as not possible.
    
    v2: fix the condition to disable FBC if PSR2 enabled (Jani)
    
    v3: use HAS_FBC_DIRTY_RECT()
    
    Bspec: 68881
    Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
+ /mt/dim checkpatch 54974a9354d844eca54feeec70870790fac17160 drm-intel
89d66f7d4021 drm/i915/xe3: add register definitions for fbc dirty rect support
-:24: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#24: FILE: drivers/gpu/drm/i915/display/intel_fbc_regs.h:107:
+#define   FBC_DIRTY_RECT_START_LINE(val)	REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val))

total: 0 errors, 1 warnings, 0 checks, 15 lines checked
e43ebe925f8e drm/i915/xe3: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect support
113bd42fe26b drm/damage-helper: add const qualifier in drm_atomic_helper_damage_merged()
19485e81fa03 drm/i915/xe3: update and store the plane damage clips
6abcfebf03fd drm/i915/xe3: dirty rect support for FBC
5cf609ededbe drm/i915/xe3: avoid calling fbc activate if fbc is active
03cef2a39845 drm/i915/xe3: disable FBC if PSR2 selective fetch is enabled