[PATCH] drm/i915/display: Add upper limit check for pixel clock

[Jani Nikula]

On Wed, 02 Jul 2025, Chaitanya Kumar Borah <chaitanya.kumar.borah at intel.com> wrote:
> Add upper limit check for pixel clock by platform. Limits don't apply
> when DSC is enabled.
>
> For the currently supported versions of HDMI, pixel clock is already
> limited to 600Mhz so nothing needs to be done there as of now.
>
> BSpec: 49199, 68912
>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah at intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++++
>  drivers/gpu/drm/i915/display/intel_display.h |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c      |  3 +++
>  3 files changed, 16 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 456fc4b04cda..bf0faff50c2e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7902,6 +7902,18 @@ void intel_setup_outputs(struct intel_display *display)
>  	drm_helper_move_panel_connectors_to_head(display->drm);
>  }
>  
> +int intel_dotclock_limit(struct intel_display *display)
> +{
> +	if (DISPLAY_VERx100(display) == 3002)
> +		return 937500;
> +	else if (DISPLAY_VER(display) >= 30)
> +		return 1350000;
> +	else if (DISPLAY_VER(display) >= 13)
> +		return 1200000;
> +	else
> +		return 1100000;
> +}

How does this relate to display->cdclk.max_dotclk_freq that's computed
in intel_compute_max_dotclk(display)?

BR,
Jani.


> +
>  static int max_dotclock(struct intel_display *display)
>  {
>  	int max_dotclock = display->cdclk.max_dotclk_freq;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 37e2ab301a80..9ad896a15ba7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -486,6 +486,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
>  				    struct intel_link_m_n *m_n);
>  int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
>  int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config);
> +int intel_dotclock_limit(struct intel_display *display);
>  enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
>  enum intel_display_power_domain
>  intel_aux_power_domain(struct intel_digital_port *dig_port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index f48912f308df..3ff2beeed801 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1507,6 +1507,9 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>  		dsc = dsc_max_compressed_bpp && dsc_slice_count;
>  	}
>  
> +	if (target_clock > (intel_dotclock_limit(display) * num_joined_pipes) && !dsc)
> +		return MODE_CLOCK_HIGH;
> +
>  	if (intel_dp_joiner_needs_dsc(display, num_joined_pipes) && !dsc)
>  		return MODE_CLOCK_HIGH;

-- 
Jani Nikula, Intel