[PATCH v3 2/7] drm/xe: Set GT as wedged before sending wedged uevent

[Raag Jadav]

On Thu, Jul 03, 2025 at 10:48:06AM +0530, Riana Tauro wrote:
> On 7/3/2025 9:48 AM, Raag Jadav wrote:
> > On Wed, Jul 02, 2025 at 07:41:12PM +0530, Riana Tauro wrote:
> > > Userspace should be notified after setting the device as wedged.
> > > Re-order function calls to set gt wedged before sending uevent.
> > > 
> > > Suggested-by: Raag Jadav <raag.jadav at intel.com>
> > > Signed-off-by: Riana Tauro <riana.tauro at intel.com>
> > > ---
> > >   drivers/gpu/drm/xe/xe_device.c | 10 ++++++----
> > >   1 file changed, 6 insertions(+), 4 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
> > > index 0b73cb72bad1..4a38486dccc8 100644
> > > --- a/drivers/gpu/drm/xe/xe_device.c
> > > +++ b/drivers/gpu/drm/xe/xe_device.c
> > > @@ -1123,8 +1123,10 @@ static void xe_device_wedged_fini(struct drm_device *drm, void *arg)
> > >    * xe_device_declare_wedged - Declare device wedged
> > >    * @xe: xe device instance
> > >    *
> > > - * This is a final state that can only be cleared with a module
> > > + * This is a final state that can only be cleared with the recovery method
> > > + * specified in the drm wedged uevent. The default recovery method is
> > >    * re-probe (unbind + bind).
> > > + *
> > >    * In this state every IOCTL will be blocked so the GT cannot be used.
> > >    * In general it will be called upon any critical error such as gt reset
> > >    * failure or guc loading failure. Userspace will be notified of this state
> > > @@ -1151,6 +1153,9 @@ void xe_device_declare_wedged(struct xe_device *xe)
> > >   		return;
> > >   	}
> > > +	for_each_gt(gt, xe, id)
> > > +		xe_gt_declare_wedged(gt);
> > 
> > This is changing GuC CT state and can race with ioctls, so I think
> > the sequence should be
> > 
> 
> Then isn't the previous flow better. The ioctls are blocked anyway before
> sending uevent.

Yes, the idea was to move the event call and not xe_gt_declare_wedged().

https://lore.kernel.org/intel-xe/aEMFcBSWL_jPMYKa@black.fi.intel.com

Raag