[PATCH 4/7] drm/xe/lrc: Add table with LRC layout

[Lucas De Marchi]

Add a table to document the LRC's BO layout to make it easier to
visualize how each region stacks on top of each other.

Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
---
 drivers/gpu/drm/xe/xe_lrc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 7cde827ddbec9..75f4678cb090a 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -42,6 +42,27 @@
 #define LRC_INDIRECT_RING_STATE_SIZE		SZ_4K
 #define LRC_WA_BB_SIZE				SZ_4K
 
+/*
+ * Layout of the LRC and associated data allocated as
+ * lrc->bo:
+ *
+ *   Region                       Size
+ *  +============================+=================+ <- __xe_lrc_ring_offset()
+ *  | Ring                       | ring_size, see  |
+ *  |                            | xe_lrc_init()   |
+ *  +============================+=================+ <- __xe_lrc_pphwsp_offset()
+ *  | PPHWSP (includes SW state) | 4K              |
+ *  +----------------------------+-----------------+ <- __xe_lrc_ring_offset()
+ *  | Engine Context Image       | n * 4K, see     |
+ *  |                            | xe_gt_lrc_size()|
+ *  +----------------------------+-----------------+ <- __xe_lrc_indirect_ring_offset()
+ *  | Indirect Ring State Page   | 0 or 4k, see    |
+ *  |                            | xe_gt_lrc_size()|
+ *  +============================+=================+ <- __xe_lrc_wa_bb_offset()
+ *  | WA BB Per Ctx              | 4k              |
+ *  +============================+=================+ <- xe_bo_size(lrc->bo)
+ */
+
 static struct xe_device *
 lrc_to_xe(struct xe_lrc *lrc)
 {

-- 
2.49.0