[PATCH v6 8/9] drm/xe/vf: Refresh utilization buffer during migration recovery
Tomasz Lis
tomasz.lis at intel.com
Fri Jul 4 21:02:27 UTC 2025
The WA buffer we use to capture context utilization contains GGTT
references. This means its instructions have to be either fixed or
re-emitted during VF post-migration recovery.
This patch adds re-emitting content of the utilization WA BB during
the recovery.
The way we write to vram requires scratch buffer to be used before
the whole block is memcopied. We are re-using a scratch buffer
introduced in earlier part of the recovery.
v2: Notable rebase after "Prepare WA BB setup for more users" patch
Signed-off-by: Tomasz Lis <tomasz.lis at intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
Cc: Michal Winiarski <michal.winiarski at intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 1 +
drivers/gpu/drm/xe/xe_lrc.c | 54 ++++++++++++++++++++----------
drivers/gpu/drm/xe/xe_lrc.h | 4 +++
drivers/gpu/drm/xe/xe_sriov_vf.c | 2 +-
4 files changed, 42 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index bd8de62cb228..ca8132c09efb 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1042,6 +1042,7 @@ void xe_exec_queue_contexts_hwsp_rebase(struct xe_exec_queue *q, void *scratch)
for (i = 0; i < q->width; ++i) {
xe_lrc_update_memirq_regs_with_address(q->lrc[i], q->hwe, scratch);
xe_lrc_update_hwctx_regs_with_address(q->lrc[i]);
+ xe_lrc_setup_wa_bb_with_scratch(q->lrc[i], q->hwe, scratch);
}
}
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 8d6cecca1e86..ca7541eba92a 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -40,7 +40,6 @@
#define LRC_PPHWSP_SIZE SZ_4K
#define LRC_INDIRECT_RING_STATE_SIZE SZ_4K
-#define LRC_WA_BB_SIZE SZ_4K
static struct xe_device *
lrc_to_xe(struct xe_lrc *lrc)
@@ -1025,25 +1024,27 @@ struct wa_bb_setup {
u32 *batch, size_t max_size);
};
-static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
+/**
+ * xe_lrc_setup_wa_bb_with_scratch - Execute all wa bb setup callbacks.
+ * @lrc: the &xe_lrc struct instance
+ * @hwe: the &xe_hw_engine struct instance
+ * @scratch: preallocated scratch buffer for temporary storage
+ * Return: 0 on success, negative error code on failure
+ */
+int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe, u32 *scratch)
{
- const size_t max_size = LRC_WA_BB_SIZE;
static const struct wa_bb_setup funcs[] = {
{ .setup = wa_bb_setup_utilization },
};
ssize_t remain;
- u32 *cmd, *buf = NULL;
+ u32 *cmd;
- if (lrc->bo->vmap.is_iomem) {
- buf = kmalloc(max_size, GFP_KERNEL);
- if (!buf)
- return -ENOMEM;
- cmd = buf;
- } else {
+ if (lrc->bo->vmap.is_iomem)
+ cmd = scratch;
+ else
cmd = lrc->bo->vmap.vaddr + __xe_lrc_wa_bb_offset(lrc);
- }
- remain = max_size / sizeof(*cmd);
+ remain = LRC_WA_BB_SIZE / sizeof(*cmd);
for (size_t i = 0; i < ARRAY_SIZE(funcs); i++) {
ssize_t len = funcs[i].setup(lrc, hwe, cmd, remain);
@@ -1062,12 +1063,10 @@ static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
*cmd++ = MI_BATCH_BUFFER_END;
- if (buf) {
+ if (lrc->bo->vmap.is_iomem)
xe_map_memcpy_to(gt_to_xe(lrc->gt), &lrc->bo->vmap,
- __xe_lrc_wa_bb_offset(lrc), buf,
- (cmd - buf) * sizeof(*cmd));
- kfree(buf);
- }
+ __xe_lrc_wa_bb_offset(lrc), scratch,
+ (cmd - scratch) * sizeof(*cmd));
xe_lrc_write_ctx_reg(lrc, CTX_BB_PER_CTX_PTR, xe_bo_ggtt_addr(lrc->bo) +
__xe_lrc_wa_bb_offset(lrc) + 1);
@@ -1075,10 +1074,29 @@ static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
return 0;
fail:
- kfree(buf);
return -ENOSPC;
}
+static int setup_wa_bb(struct xe_lrc *lrc, struct xe_hw_engine *hwe)
+{
+ const size_t max_size = LRC_WA_BB_SIZE;
+ u32 *buf = NULL;
+ int ret;
+
+ if (lrc->bo->vmap.is_iomem) {
+ buf = kmalloc(max_size, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+ }
+
+ ret = xe_lrc_setup_wa_bb_with_scratch(lrc, hwe, buf);
+
+ if (lrc->bo->vmap.is_iomem)
+ kfree(buf);
+
+ return ret;
+}
+
#define PVC_CTX_ASID (0x2e + 1)
#define PVC_CTX_ACC_CTR_THOLD (0x2a + 1)
diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h
index a6205077f024..04e222e23d8d 100644
--- a/drivers/gpu/drm/xe/xe_lrc.h
+++ b/drivers/gpu/drm/xe/xe_lrc.h
@@ -42,6 +42,8 @@ struct xe_lrc_snapshot {
#define LRC_PPHWSP_FLUSH_INVAL_SCRATCH_ADDR (0x34 * 4)
#define LRC_PPHWSP_PXP_INVAL_SCRATCH_ADDR (0x40 * 4)
+#define LRC_WA_BB_SIZE SZ_4K
+
#define XE_LRC_CREATE_RUNALONE 0x1
#define XE_LRC_CREATE_PXP 0x2
struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
@@ -129,6 +131,8 @@ u32 xe_lrc_ctx_timestamp_udw_ggtt_addr(struct xe_lrc *lrc);
u64 xe_lrc_ctx_timestamp(struct xe_lrc *lrc);
u32 xe_lrc_ctx_job_timestamp_ggtt_addr(struct xe_lrc *lrc);
u32 xe_lrc_ctx_job_timestamp(struct xe_lrc *lrc);
+int xe_lrc_setup_wa_bb_with_scratch(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
+ u32 *scratch);
/**
* xe_lrc_update_timestamp - readout LRC timestamp and update cached value
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf.c b/drivers/gpu/drm/xe/xe_sriov_vf.c
index a219395c15de..a4927b0792b5 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf.c
@@ -247,7 +247,7 @@ static int vf_get_next_migrated_gt_id(struct xe_device *xe)
static size_t post_migration_scratch_size(struct xe_device *xe)
{
- return xe_lrc_reg_size(xe);
+ return max(xe_lrc_reg_size(xe), LRC_WA_BB_SIZE);
}
/**
--
2.25.1
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