[PATCH] drm/xe: Rename MCFG_MCR_SELECTOR to STEER_SEMAPHORE
Upadhyay, Tejas
tejas.upadhyay at intel.com
Wed Jul 23 12:57:30 UTC 2025
> -----Original Message-----
> From: Gote, Nitin R <nitin.r.gote at intel.com>
> Sent: 23 July 2025 15:52
> To: intel-xe at lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi at intel.com>; Upadhyay, Tejas
> <tejas.upadhyay at intel.com>; Gote, Nitin R <nitin.r.gote at intel.com>
> Subject: [PATCH] drm/xe: Rename MCFG_MCR_SELECTOR to
> STEER_SEMAPHORE
>
> The register at offset 0xfd0 was incorrectly named MCFG_MCR_SELECTOR,
> likely copied from i915. According to the hardware specification (bspec), this
> register is actually called STEER_SEMAPHORE.
Can you mention # please
Tejas
>
> Rename the register definition and update its usage in xe_gt_mcr.c to match
> the official hardware documentation.
>
> No functional changes.
>
> Signed-off-by: Nitin Gote <nitin.r.gote at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
> drivers/gpu/drm/xe/xe_gt_mcr.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 5cd5ab8529c5..f96b2e2b3064 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -42,7 +42,7 @@
> #define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
> #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc)
>
> -#define MCFG_MCR_SELECTOR XE_REG(0xfd0)
> +#define STEER_SEMAPHORE XE_REG(0xfd0)
> #define MTL_MCR_SELECTOR XE_REG(0xfd4)
> #define SF_MCR_SELECTOR XE_REG(0xfd8)
> #define MCR_SELECTOR XE_REG(0xfdc)
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c
> b/drivers/gpu/drm/xe/xe_gt_mcr.c index 64a2f0d6aaf9..ca27b9dc92cc
> 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -533,7 +533,7 @@ void xe_gt_mcr_set_implicit_defaults(struct xe_gt
> *gt)
> u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |
> REG_FIELD_PREP(MCR_SUBSLICE_MASK, 2);
>
> - xe_mmio_write32(>->mmio, MCFG_MCR_SELECTOR,
> steer_val);
> + xe_mmio_write32(>->mmio, STEER_SEMAPHORE,
> steer_val);
> xe_mmio_write32(>->mmio, SF_MCR_SELECTOR,
> steer_val);
> /*
> * For GAM registers, all reads should be directed to instance 1
> --
> 2.25.1
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