[PATCH v2 5/6] drm/xe/migrate: Populate struct drm_pagemap_addr array

[Matthew Brost]

On Fri, Jul 25, 2025 at 05:39:29PM +0200, Francois Dugast wrote:
> Ensure all addresses are populated in the array as this is expected
> when creating the copy batch.
> 
> Signed-off-by: Francois Dugast <francois.dugast at intel.com>

Nice, this looks like the correct place to W/A the migrate layer not yet
support 2M GPU pages.

I have something for this locally and will post after this series
merges. Maybe meantion in commit message a follow up properly fix this
one.

This patch LGTM, with that:
Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_migrate.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index c33bd1b139c9..998b37852ac7 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -1797,6 +1797,7 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m,
>  	unsigned int pitch = len >= PAGE_SIZE && !(len & ~PAGE_MASK) ?
>  		PAGE_SIZE : 4;
>  	int err;
> +	unsigned long i, j;
>  
>  	if (drm_WARN_ON(&xe->drm, (len & XE_CACHELINE_MASK) ||
>  			(sram_offset | vram_addr) & XE_CACHELINE_MASK))
> @@ -1813,6 +1814,24 @@ static struct dma_fence *xe_migrate_vram(struct xe_migrate *m,
>  		return ERR_PTR(err);
>  	}
>  
> +	/*
> +	 * If the order of a struct drm_pagemap_addr entry is greater than 0,
> +	 * the entry is populated by GPU pagemap but subsequent entries within
> +	 * the range of that order are not populated.
> +	 * build_pt_update_batch_sram() expects a fully populated array of
> +	 * struct drm_pagemap_addr. Ensure this is the case even with higher
> +	 * orders.
> +	 */
> +	for (i = 0; i < npages;) {
> +		unsigned int order = sram_addr[i].order;
> +
> +		for (j = 1; j < NR_PAGES(order) && i + j < npages; j++)
> +			if (!sram_addr[i + j].addr)
> +				sram_addr[i + j].addr = sram_addr[i].addr + j * PAGE_SIZE;
> +
> +		i += NR_PAGES(order);
> +	}
> +
>  	build_pt_update_batch_sram(m, bb, pt_slot * XE_PAGE_SIZE,
>  				   sram_addr, len + sram_offset);
>  
> -- 
> 2.43.0
>