[PATCH v5 11/23] drm/xe/svm : Add svm ranges migration policy on atomic access
Ghimiray, Himal Prasad
himal.prasad.ghimiray at intel.com
Wed Jul 30 04:59:11 UTC 2025
On 29-07-2025 09:34, Matthew Brost wrote:
> On Tue, Jul 22, 2025 at 07:05:14PM +0530, Himal Prasad Ghimiray wrote:
>> If the platform does not support atomic access on system memory, and the
>> ranges are in system memory, but the user requires atomic accesses on
>> the VMA, then migrate the ranges to VRAM. Apply this policy for prefetch
>> operations as well.
>>
>> v2
>> - Drop unnecessary vm_dbg
>>
>> v3 (Matthew Brost)
>> - fix atomic policy
>> - prefetch shouldn't have any impact of atomic
>> - bo can be accessed from vma, avoid duplicate parameter
>>
>> v4 (Matthew Brost)
>> - Remove TODO comment
>> - Fix comment
>> - Dont allow gpu atomic ops when user is setting atomic attr as CPU
>>
>> Cc: Matthew Brost <matthew.brost at intel.com>
>> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_pt.c | 23 +++++++++--------
>> drivers/gpu/drm/xe/xe_svm.c | 2 +-
>> drivers/gpu/drm/xe/xe_vm.c | 40 ++++++++++++++++++++++++++++++
>> drivers/gpu/drm/xe/xe_vm.h | 2 ++
>> drivers/gpu/drm/xe/xe_vm_madvise.c | 9 ++++++-
>> 5 files changed, 64 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
>> index b499006df2cf..96d0ffe8154e 100644
>> --- a/drivers/gpu/drm/xe/xe_pt.c
>> +++ b/drivers/gpu/drm/xe/xe_pt.c
>> @@ -640,28 +640,31 @@ static const struct xe_pt_walk_ops xe_pt_stage_bind_ops = {
>> * - In all other cases device atomics will be disabled with AE=0 until an application
>> * request differently using a ioctl like madvise.
>> */
>> -static bool xe_atomic_for_vram(struct xe_vm *vm)
>> +static bool xe_atomic_for_vram(struct xe_vm *vm, struct xe_vma *vma)
>> {
>> + if (vma->attr.atomic_access == DRM_XE_ATOMIC_CPU)
>> + return false;
>> +
>> return true;
>> }
>>
>> -static bool xe_atomic_for_system(struct xe_vm *vm, struct xe_bo *bo)
>> +static bool xe_atomic_for_system(struct xe_vm *vm, struct xe_vma *vma)
>> {
>> struct xe_device *xe = vm->xe;
>> + struct xe_bo *bo = xe_vma_bo(vma);
>>
>> - if (!xe->info.has_device_atomics_on_smem)
>> + if (!xe->info.has_device_atomics_on_smem ||
>> + vma->attr.atomic_access == DRM_XE_ATOMIC_CPU)
>> return false;
>>
>> + if (vma->attr.atomic_access == DRM_XE_ATOMIC_DEVICE)
>> + return true;
>> +
>> /*
>> * If a SMEM+LMEM allocation is backed by SMEM, a device
>> * atomics will cause a gpu page fault and which then
>> * gets migrated to LMEM, bind such allocations with
>> * device atomics enabled.
>> - *
>> - * TODO: Revisit this. Perhaps add something like a
>> - * fault_on_atomics_in_system UAPI flag.
>> - * Note that this also prohibits GPU atomics in LR mode for
>> - * userptr and system memory on DGFX.
>> */
>> return (!IS_DGFX(xe) || (!xe_vm_in_lr_mode(vm) ||
>> (bo && xe_bo_has_single_placement(bo))));
>> @@ -744,8 +747,8 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
>> goto walk_pt;
>>
>> if (vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT) {
>> - xe_walk.default_vram_pte = xe_atomic_for_vram(vm) ? XE_USM_PPGTT_PTE_AE : 0;
>> - xe_walk.default_system_pte = xe_atomic_for_system(vm, bo) ?
>> + xe_walk.default_vram_pte = xe_atomic_for_vram(vm, vma) ? XE_USM_PPGTT_PTE_AE : 0;
>> + xe_walk.default_system_pte = xe_atomic_for_system(vm, vma) ?
>> XE_USM_PPGTT_PTE_AE : 0;
>> }
>>
>> diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c
>> index c093dc453e32..49d3405aacb9 100644
>> --- a/drivers/gpu/drm/xe/xe_svm.c
>> +++ b/drivers/gpu/drm/xe/xe_svm.c
>> @@ -813,7 +813,7 @@ int xe_svm_handle_pagefault(struct xe_vm *vm, struct xe_vma *vma,
>> IS_ENABLED(CONFIG_DRM_XE_PAGEMAP),
>> .check_pages_threshold = IS_DGFX(vm->xe) &&
>> IS_ENABLED(CONFIG_DRM_XE_PAGEMAP) ? SZ_64K : 0,
>> - .devmem_only = atomic && IS_DGFX(vm->xe) &&
>> + .devmem_only = xe_vma_need_vram_for_atomic(vm->xe, vma, atomic) &&
>> IS_ENABLED(CONFIG_DRM_XE_PAGEMAP),
>> .timeslice_ms = atomic && IS_DGFX(vm->xe) &&
>> IS_ENABLED(CONFIG_DRM_XE_PAGEMAP) ?
>> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
>> index 7f3d0ad04b3f..be51fcf322ec 100644
>> --- a/drivers/gpu/drm/xe/xe_vm.c
>> +++ b/drivers/gpu/drm/xe/xe_vm.c
>> @@ -4177,6 +4177,46 @@ void xe_vm_snapshot_free(struct xe_vm_snapshot *snap)
>> kvfree(snap);
>> }
>>
>> +/**
>> + * xe_vma_need_vram_for_atomic - Check if VMA needs VRAM migration for atomic operations
>> + * @xe: Pointer to the XE device structure
>> + * @vma: Pointer to the virtual memory area (VMA) structure
>> + * @is_atomic: In pagefault path and atomic operation
>> + *
>> + * This function determines whether the given VMA needs to be migrated to
>> + * VRAM in order to do atomic GPU operation.
>> + *
>> + * Return: true if migration to VRAM is required, false otherwise.
>> + */
>> +bool xe_vma_need_vram_for_atomic(struct xe_device *xe, struct xe_vma *vma, bool is_atomic)
>> +{
>> + if (!IS_DGFX(xe))
>> + return false;
>> +
>> + /*
>> + * NOTE: The checks implemented here are platform-specific. For
>> + * instance, on a device supporting CXL atomics, these would ideally
>> + * work universally without additional handling.
>> + */
>> + switch (vma->attr.atomic_access) {
>> + case DRM_XE_ATOMIC_DEVICE:
>> + return !xe->info.has_device_atomics_on_smem;
>
> I think this is is_atomic && !xe->info.has_device_atomics_on_smem;
>
> We really only want strick migration if the fault is an atomic one.
>
>> +
>> + case DRM_XE_ATOMIC_CPU:
>> + XE_WARN_ON(is_atomic);
>
> I think we should nack the fault if an atomic occurs and
> DRM_XE_ATOMIC_CPU is set - both for SVMs and BOs.
>
>> + return false;
>> +
>> + case DRM_XE_ATOMIC_UNDEFINED:
>> + return is_atomic;
>> +
>> + case DRM_XE_ATOMIC_GLOBAL:
>> + return true;
>
> As with above, I think this is is_atomic to only implement strick
> migration on atomic faults.
Agreed to all above comments. Will fix in next rev
>
> Matt
>
>> +
>> + default:
>> + return is_atomic;
>> + }
>> +}
>> +
>> /**
>> * xe_vm_alloc_madvise_vma - Allocate VMA's with madvise ops
>> * @vm: Pointer to the xe_vm structure
>> diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h
>> index 0d6b08cc4163..d5bc09ae640c 100644
>> --- a/drivers/gpu/drm/xe/xe_vm.h
>> +++ b/drivers/gpu/drm/xe/xe_vm.h
>> @@ -171,6 +171,8 @@ static inline bool xe_vma_is_userptr(struct xe_vma *vma)
>>
>> struct xe_vma *xe_vm_find_vma_by_addr(struct xe_vm *vm, u64 page_addr);
>>
>> +bool xe_vma_need_vram_for_atomic(struct xe_device *xe, struct xe_vma *vma, bool is_atomic);
>> +
>> int xe_vm_alloc_madvise_vma(struct xe_vm *vm, uint64_t addr, uint64_t size);
>>
>> /**
>> diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
>> index f64728120d7c..62dc5cec8950 100644
>> --- a/drivers/gpu/drm/xe/xe_vm_madvise.c
>> +++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
>> @@ -85,7 +85,14 @@ static void madvise_atomic(struct xe_device *xe, struct xe_vm *vm,
>> struct xe_vma **vmas, int num_vmas,
>> struct drm_xe_madvise *op)
>> {
>> - /* Implementation pending */
>> + int i;
>> +
>> + xe_assert(vm->xe, op->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC);
>> + xe_assert(vm->xe, op->atomic.val <= DRM_XE_ATOMIC_CPU);
>> +
>> + for (i = 0; i < num_vmas; i++)
>> + vmas[i]->attr.atomic_access = op->atomic.val;
>> + /*TODO: handle bo backed vmas */
>> }
>>
>> static void madvise_pat_index(struct xe_device *xe, struct xe_vm *vm,
>> --
>> 2.34.1
>>
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