✓ CI.checkpatch: success for drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup (rev2)
URL   : https://patchwork.freedesktop.org/series/149566/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
202708c00696422fd217223bb679a353a5936e23
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit f297be99936fbe156d2494013fd835b718b29e61
Author: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian at intel.com>
Date:   Wed May 28 12:15:56 2025 +0530

    drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup
    
    When configuring the HDMI PLL, calculations use DIV_ROUND_UP_ULL and
    DIV_ROUND_DOWN_ULL macros, which internally rely on do_div. However, do_div
    expects a 32-bit (u32) divisor, and at higher data rates, the divisor can
    exceed this limit. This leads to incorrect division results and
    ultimately misconfigured PLL values.
    This fix replaces do_div calls with  div64_base64 calls where diviser
    can exceed u32 limit.
    
    Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian at intel.com>
    Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
    Fixes: 5947642004bf ("drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2")
    Cc: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
    Cc: Suraj Kandpal <suraj.kandpal at intel.com>
    Cc: Jani Nikula <jani.nikula at intel.com>
+ /mt/dim checkpatch 574ad1700b1819b1e762e9ab2a708ea100b4ba97 drm-intel
f297be99936f drm/i915/display: Fix u32 overflow in SNPS PHY HDMI PLL setup