[PATCH v6 16/17] drm/i915/display: Add function to configure PIPEDMC_EVT_CTL

[Nautiyal, Ankit K]

On 6/4/2025 1:05 AM, Mitul Golani wrote:
> Configure PIPEDMC_EVT_CTL_3 register with required event flags.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani at intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dmc.c | 20 ++++++++++++++++++++
>   drivers/gpu/drm/i915/display/intel_dmc.h |  2 ++
>   drivers/gpu/drm/i915/display/intel_vrr.c |  8 ++++++--
>   3 files changed, 28 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 13652dd1ed2a..7c55334814e7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -618,6 +618,26 @@ void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
>   		     PIPEDMC_BLOCK_PKGC_SW_BLOCK_PKGC_ALWAYS : 0);
>   }
>   
> +void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
> +					     enum pipe pipe, bool enable)
> +{
> +	u32 val;
> +
> +	if (enable)
> +		val = DMC_EVT_CTL_ENABLE | DMC_EVT_CTL_RECURRING |
> +			REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> +				       DMC_EVT_CTL_TYPE_EDGE_0_1) |
> +			REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> +				       PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER);
> +	else
> +		val = REG_FIELD_PREP(DMC_EVT_CTL_EVENT_ID_MASK,
> +				     DMC_EVENT_FALSE) |
> +		      REG_FIELD_PREP(DMC_EVT_CTL_TYPE_MASK,
> +				     DMC_EVT_CTL_TYPE_EDGE_0_1);

Do we need to set bit DMC_EVT_CTL_TYPE_EDGE_0_1 for both enable/disable 
case.

If we do then perhaps `val` can be initialized with this value.

Regards,

Ankit

> +
> +	intel_de_write(display, PIPEDMC_EVT_CTL_3(pipe), val);
> +}
> +
>   /**
>    * intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank() - start of PKG
>    * C-state exit
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 12912e80bbc6..e7a46e00caf1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -22,6 +22,8 @@ void intel_dmc_enable_pipe(struct intel_display *display, enum pipe pipe);
>   void intel_dmc_disable_pipe(struct intel_display *display, enum pipe pipe);
>   void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe,
>   			  bool block);
> +void intel_dmc_configure_dc_balance_ctl_regs(struct intel_display *display,
> +					     enum pipe pipe, bool enable);
>   void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display,
>   							    enum pipe pipe, bool enable);
>   void intel_dmc_fini(struct intel_display *display);
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9cc6898399e4..068fa7e792ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -687,8 +687,10 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
>   
>   	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), ctl);
>   
> -	if (crtc_state->vrr.dc_balance.enable)
> +	if (crtc_state->vrr.dc_balance.enable) {
> +		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, true);
>   		intel_pipedmc_dcb_enable(NULL, crtc);
> +	}
>   }
>   
>   void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
> @@ -702,8 +704,10 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
>   	if (!old_crtc_state->vrr.enable)
>   		return;
>   
> -	if (old_crtc_state->vrr.dc_balance.enable)
> +	if (old_crtc_state->vrr.dc_balance.enable) {
>   		intel_pipedmc_dcb_disable(NULL, crtc);
> +		intel_dmc_configure_dc_balance_ctl_regs(display, pipe, false);
> +	}
>   
>   	ctl = trans_vrr_ctl(old_crtc_state);
>   	if (intel_vrr_always_use_vrr_tg(display))