[PATCH] drm/xe: Add ASID to range invalidation feature flag

[Upadhyay, Tejas]

> -----Original Message-----
> From: Summers, Stuart <stuart.summers at intel.com>
> Sent: 03 June 2025 22:40
> To: Upadhyay, Tejas <tejas.upadhyay at intel.com>
> Cc: intel-xe at lists.freedesktop.org; Vishwanathapura, Niranjana
> <niranjana.vishwanathapura at intel.com>
> Subject: Re: [PATCH] drm/xe: Add ASID to range invalidation feature flag
> 
> On Tue, 2025-06-03 at 08:49 +0000, Upadhyay, Tejas wrote:
> >
> >
> > > -----Original Message-----
> > > From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of
> > > Stuart Summers
> > > Sent: 01 May 2025 23:06
> > > Cc: Vishwanathapura, Niranjana
> > > <niranjana.vishwanathapura at intel.com>;
> > > intel-xe at lists.freedesktop.org; Summers, Stuart
> > > <stuart.summers at intel.com>
> > > Subject: [PATCH] drm/xe: Add ASID to range invalidation feature flag
> > >
> > > Make it explicit that the ASID is used to identify a VM when issuing
> > > a ranged- based TLB invalidation.
> > >
> > > /s/has_range_tlb_invalidation/has_range_tlb_invalidation_asid/
> >
> > While the patch looks ok, what is the motivation, is that guc doing
> > asid based invalidation now so changing flag name?
> 
> This is more about clarification. We might also have a time where we want to
> be able to do invalidations triggered at some finer granularity than by
> process/asid, so this gives the clarification on the intention.
> 
> Thanks,
> Stuart
> 
> >
> > Tejas
> > >
> > > Signed-off-by: Stuart Summers <stuart.summers at intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/xe_device_types.h        | 4 ++--
> > >  drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c | 2 +-
> > >  drivers/gpu/drm/xe/xe_pci.c                 | 6 +++---
> > >  drivers/gpu/drm/xe/xe_pci_types.h           | 2 +-
> > >  4 files changed, 7 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h
> > > b/drivers/gpu/drm/xe/xe_device_types.h
> > > index 06c65dace026..3e49b88a8a62 100644
> > > --- a/drivers/gpu/drm/xe/xe_device_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_device_types.h
> > > @@ -327,8 +327,8 @@ struct xe_device {
> > >                 u8 has_llc:1;
> > >                 /** @info.has_pxp: Device has PXP support */
> > >                 u8 has_pxp:1;
> > > -               /** @info.has_range_tlb_invalidation: Has range
> > > based TLB invalidations */
> > > -               u8 has_range_tlb_invalidation:1;
> > > +               /** @info.has_range_tlb_invalidation_asid: Has
> > > range based
> > > TLB invalidations */

Can we add per asid here

However, change looks good ok to me,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

Tejas
> > > +               u8 has_range_tlb_invalidation_asid:1;
> > >                 /** @info.has_sriov: Supports SR-IOV */
> > >                 u8 has_sriov:1;
> > >                 /** @info.has_usm: Device has unified shared memory
> > > support */ diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> > > b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> > > index 084cbdeba8ea..c68f7cc8e175 100644
> > > --- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> > > +++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.c
> > > @@ -366,7 +366,7 @@ int xe_gt_tlb_invalidation_range(struct xe_gt
> > > *gt,
> > >
> > >         action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;
> > >         action[len++] = 0; /* seqno, replaced in
> > > send_tlb_invalidation */
> > > -       if (!xe->info.has_range_tlb_invalidation ||
> > > +       if (!xe->info.has_range_tlb_invalidation_asid ||
> > >             length > MAX_RANGE_TLB_INVALIDATION_LENGTH) {
> > >                 action[len++] =
> > > MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);
> > >         } else {
> > > diff --git a/drivers/gpu/drm/xe/xe_pci.c
> > > b/drivers/gpu/drm/xe/xe_pci.c index
> > > a4caa6222b6f..cfafcfcbbbc6 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci.c
> > > +++ b/drivers/gpu/drm/xe/xe_pci.c
> > > @@ -91,7 +91,7 @@ static const struct xe_graphics_desc graphics_xelp
> > > = {  };
> > >
> > >  #define XE_HP_FEATURES \
> > > -       .has_range_tlb_invalidation = true, \
> > > +       .has_range_tlb_invalidation_asid = true, \
> > >         .va_bits = 48, \
> > >         .vm_max_level = 3
> > >
> > > @@ -140,7 +140,7 @@ static const struct xe_graphics_desc
> > > graphics_xelpg = {
> > >         .has_atomic_enable_pte_bit = 1, \
> > >         .has_flat_ccs = 1, \
> > >         .has_indirect_ring_state = 1, \
> > > -       .has_range_tlb_invalidation = 1, \
> > > +       .has_range_tlb_invalidation_asid = 1, \
> > >         .has_usm = 1, \
> > >         .va_bits = 48, \
> > >         .vm_max_level = 4, \
> > > @@ -680,7 +680,7 @@ static int xe_info_init(struct xe_device *xe,
> > >         /* Runtime detection may change this later */
> > >         xe->info.has_flat_ccs = graphics_desc->has_flat_ccs;
> > >
> > > -       xe->info.has_range_tlb_invalidation = graphics_desc-
> > > > has_range_tlb_invalidation;
> > > +       xe->info.has_range_tlb_invalidation_asid =
> > > +graphics_desc->has_range_tlb_invalidation_asid;
> > >         xe->info.has_usm = graphics_desc->has_usm;
> > >
> > >         for_each_remote_tile(tile, xe, id) { diff --git
> > > a/drivers/gpu/drm/xe/xe_pci_types.h
> > > b/drivers/gpu/drm/xe/xe_pci_types.h
> > > index e9b9bbc138d3..3d1c745de2ac 100644
> > > --- a/drivers/gpu/drm/xe/xe_pci_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_pci_types.h
> > > @@ -19,7 +19,7 @@ struct xe_graphics_desc {
> > >         u8 has_atomic_enable_pte_bit:1;
> > >         u8 has_flat_ccs:1;
> > >         u8 has_indirect_ring_state:1;
> > > -       u8 has_range_tlb_invalidation:1;
> > > +       u8 has_range_tlb_invalidation_asid:1;
> > >         u8 has_usm:1;
> > >  };
> > >
> > > --
> > > 2.34.1
> >