[PATCH 3/4] drm/xe: Promote struct xe_tile definition to own file

[Matt Roper]

On Tue, Jun 03, 2025 at 10:28:25PM +0200, Michal Wajdeczko wrote:
> We already have separate .c and .h files for xe_tile functions,
> time to introduce _types.h to follow what other components do.

Solely looking at today's code this movement makes sense, but looking
forward it might make sense to put the vram region in its own header
since it likely won't always be as closely tied to a tile.  See, for
example, this in-flight patch which is breaking some of the hard-coded
relationship between tile/vram:

https://lore.kernel.org/all/20250528074743.2027563-2-piotr.piorkowski@intel.com/


Matt

> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Matt Roper <matthew.d.roper at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_device_types.h | 159 +------------------------
>  drivers/gpu/drm/xe/xe_tile_types.h   | 172 +++++++++++++++++++++++++++
>  2 files changed, 173 insertions(+), 158 deletions(-)
>  create mode 100644 drivers/gpu/drm/xe/xe_tile_types.h
> 
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 831dd88a4c52..c9401acb6710 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -10,14 +10,10 @@
>  
>  #include <drm/drm_device.h>
>  #include <drm/drm_file.h>
> -#include <drm/drm_pagemap.h>
>  #include <drm/ttm/ttm_device.h>
>  
>  #include "xe_devcoredump_types.h"
>  #include "xe_heci_gsc.h"
> -#include "xe_lmtt_types.h"
> -#include "xe_memirq_types.h"
> -#include "xe_mmio_types.h"
>  #include "xe_oa_types.h"
>  #include "xe_platform_types.h"
>  #include "xe_pmu_types.h"
> @@ -25,14 +21,13 @@
>  #include "xe_sriov_types.h"
>  #include "xe_step_types.h"
>  #include "xe_survivability_mode_types.h"
> -#include "xe_ttm_vram_mgr_types.h"
> +#include "xe_tile_types.h"
>  
>  #if IS_ENABLED(CONFIG_DRM_XE_DEBUG)
>  #define TEST_VM_OPS_ERROR
>  #endif
>  
>  struct intel_display;
> -struct xe_ggtt;
>  struct xe_pat_ops;
>  struct xe_pxp;
>  
> @@ -62,158 +57,6 @@ struct xe_pxp;
>  	 (_xe)->info.step.graphics >= (min_step) &&			\
>  	 (_xe)->info.step.graphics < (max_step))
>  
> -#define tile_to_xe(tile__)								\
> -	_Generic(tile__,								\
> -		 const struct xe_tile * : (const struct xe_device *)((tile__)->xe),	\
> -		 struct xe_tile * : (tile__)->xe)
> -
> -/**
> - * struct xe_vram_region - memory region structure
> - * This is used to describe a memory region in xe
> - * device, such as HBM memory or CXL extension memory.
> - */
> -struct xe_vram_region {
> -	/** @io_start: IO start address of this VRAM instance */
> -	resource_size_t io_start;
> -	/**
> -	 * @io_size: IO size of this VRAM instance
> -	 *
> -	 * This represents how much of this VRAM we can access
> -	 * via the CPU through the VRAM BAR. This can be smaller
> -	 * than @usable_size, in which case only part of VRAM is CPU
> -	 * accessible (typically the first 256M). This
> -	 * configuration is known as small-bar.
> -	 */
> -	resource_size_t io_size;
> -	/** @dpa_base: This memory regions's DPA (device physical address) base */
> -	resource_size_t dpa_base;
> -	/**
> -	 * @usable_size: usable size of VRAM
> -	 *
> -	 * Usable size of VRAM excluding reserved portions
> -	 * (e.g stolen mem)
> -	 */
> -	resource_size_t usable_size;
> -	/**
> -	 * @actual_physical_size: Actual VRAM size
> -	 *
> -	 * Actual VRAM size including reserved portions
> -	 * (e.g stolen mem)
> -	 */
> -	resource_size_t actual_physical_size;
> -	/** @mapping: pointer to VRAM mappable space */
> -	void __iomem *mapping;
> -	/** @ttm: VRAM TTM manager */
> -	struct xe_ttm_vram_mgr ttm;
> -#if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
> -	/** @pagemap: Used to remap device memory as ZONE_DEVICE */
> -	struct dev_pagemap pagemap;
> -	/**
> -	 * @dpagemap: The struct drm_pagemap of the ZONE_DEVICE memory
> -	 * pages of this tile.
> -	 */
> -	struct drm_pagemap dpagemap;
> -	/**
> -	 * @hpa_base: base host physical address
> -	 *
> -	 * This is generated when remap device memory as ZONE_DEVICE
> -	 */
> -	resource_size_t hpa_base;
> -#endif
> -};
> -
> -/**
> - * struct xe_tile - hardware tile structure
> - *
> - * From a driver perspective, a "tile" is effectively a complete GPU, containing
> - * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
> - *
> - * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
> - * device and designate one "root" tile as being responsible for external PCI
> - * communication.  PCI BAR0 exposes the GGTT and MMIO register space for each
> - * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
> - * with each tile similarly.  Device-wide interrupts can be enabled/disabled
> - * at the root tile, and the MSTR_TILE_INTR register will report which tiles
> - * have interrupts that need servicing.
> - */
> -struct xe_tile {
> -	/** @xe: Backpointer to tile's PCI device */
> -	struct xe_device *xe;
> -
> -	/** @id: ID of the tile */
> -	u8 id;
> -
> -	/**
> -	 * @primary_gt: Primary GT
> -	 */
> -	struct xe_gt *primary_gt;
> -
> -	/**
> -	 * @media_gt: Media GT
> -	 *
> -	 * Only present on devices with media version >= 13.
> -	 */
> -	struct xe_gt *media_gt;
> -
> -	/**
> -	 * @mmio: MMIO info for a tile.
> -	 *
> -	 * Each tile has its own 16MB space in BAR0, laid out as:
> -	 * * 0-4MB: registers
> -	 * * 4MB-8MB: reserved
> -	 * * 8MB-16MB: global GTT
> -	 */
> -	struct xe_mmio mmio;
> -
> -	/** @mem: memory management info for tile */
> -	struct {
> -		/**
> -		 * @mem.vram: VRAM info for tile.
> -		 *
> -		 * Although VRAM is associated with a specific tile, it can
> -		 * still be accessed by all tiles' GTs.
> -		 */
> -		struct xe_vram_region vram;
> -
> -		/** @mem.ggtt: Global graphics translation table */
> -		struct xe_ggtt *ggtt;
> -
> -		/**
> -		 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
> -		 *
> -		 * Media GT shares a pool with its primary GT.
> -		 */
> -		struct xe_sa_manager *kernel_bb_pool;
> -	} mem;
> -
> -	/** @sriov: tile level virtualization data */
> -	union {
> -		struct {
> -			/** @sriov.pf.lmtt: Local Memory Translation Table. */
> -			struct xe_lmtt lmtt;
> -		} pf;
> -		struct {
> -			/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
> -			struct xe_ggtt_node *ggtt_balloon[2];
> -		} vf;
> -	} sriov;
> -
> -	/** @memirq: Memory Based Interrupts. */
> -	struct xe_memirq memirq;
> -
> -	/** @pcode: tile's PCODE */
> -	struct {
> -		/** @pcode.lock: protecting tile's PCODE mailbox data */
> -		struct mutex lock;
> -	} pcode;
> -
> -	/** @migrate: Migration helper for vram blits and clearing */
> -	struct xe_migrate *migrate;
> -
> -	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
> -	struct kobject *sysfs;
> -};
> -
>  /**
>   * struct xe_device - Top level struct of XE device
>   */
> diff --git a/drivers/gpu/drm/xe/xe_tile_types.h b/drivers/gpu/drm/xe/xe_tile_types.h
> new file mode 100644
> index 000000000000..572b6c4b651d
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_tile_types.h
> @@ -0,0 +1,172 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022-2025 Intel Corporation
> + */
> +
> +#ifndef _XE_TILE_TYPES_H_
> +#define _XE_TILE_TYPES_H_
> +
> +#include <drm/drm_pagemap.h>
> +
> +#include "xe_lmtt_types.h"
> +#include "xe_memirq_types.h"
> +#include "xe_mmio_types.h"
> +#include "xe_ttm_vram_mgr_types.h"
> +
> +struct xe_device;
> +struct xe_ggtt;
> +struct xe_gt;
> +
> +#define tile_to_xe(tile__)								\
> +	_Generic(tile__,								\
> +		 const struct xe_tile * : (const struct xe_device *)((tile__)->xe),	\
> +		 struct xe_tile * : (tile__)->xe)
> +
> +/**
> + * struct xe_vram_region - memory region structure
> + * This is used to describe a memory region in xe
> + * device, such as HBM memory or CXL extension memory.
> + */
> +struct xe_vram_region {
> +	/** @io_start: IO start address of this VRAM instance */
> +	resource_size_t io_start;
> +	/**
> +	 * @io_size: IO size of this VRAM instance
> +	 *
> +	 * This represents how much of this VRAM we can access
> +	 * via the CPU through the VRAM BAR. This can be smaller
> +	 * than @usable_size, in which case only part of VRAM is CPU
> +	 * accessible (typically the first 256M). This
> +	 * configuration is known as small-bar.
> +	 */
> +	resource_size_t io_size;
> +	/** @dpa_base: This memory regions's DPA (device physical address) base */
> +	resource_size_t dpa_base;
> +	/**
> +	 * @usable_size: usable size of VRAM
> +	 *
> +	 * Usable size of VRAM excluding reserved portions
> +	 * (e.g stolen mem)
> +	 */
> +	resource_size_t usable_size;
> +	/**
> +	 * @actual_physical_size: Actual VRAM size
> +	 *
> +	 * Actual VRAM size including reserved portions
> +	 * (e.g stolen mem)
> +	 */
> +	resource_size_t actual_physical_size;
> +	/** @mapping: pointer to VRAM mappable space */
> +	void __iomem *mapping;
> +	/** @ttm: VRAM TTM manager */
> +	struct xe_ttm_vram_mgr ttm;
> +#if IS_ENABLED(CONFIG_DRM_XE_DEVMEM_MIRROR)
> +	/** @pagemap: Used to remap device memory as ZONE_DEVICE */
> +	struct dev_pagemap pagemap;
> +	/**
> +	 * @dpagemap: The struct drm_pagemap of the ZONE_DEVICE memory
> +	 * pages of this tile.
> +	 */
> +	struct drm_pagemap dpagemap;
> +	/**
> +	 * @hpa_base: base host physical address
> +	 *
> +	 * This is generated when remap device memory as ZONE_DEVICE
> +	 */
> +	resource_size_t hpa_base;
> +#endif
> +};
> +
> +/**
> + * struct xe_tile - hardware tile structure
> + *
> + * From a driver perspective, a "tile" is effectively a complete GPU, containing
> + * an SGunit, 1-2 GTs, and (for discrete platforms) VRAM.
> + *
> + * Multi-tile platforms effectively bundle multiple GPUs behind a single PCI
> + * device and designate one "root" tile as being responsible for external PCI
> + * communication.  PCI BAR0 exposes the GGTT and MMIO register space for each
> + * tile in a stacked layout, and PCI BAR2 exposes the local memory associated
> + * with each tile similarly.  Device-wide interrupts can be enabled/disabled
> + * at the root tile, and the MSTR_TILE_INTR register will report which tiles
> + * have interrupts that need servicing.
> + */
> +struct xe_tile {
> +	/** @xe: Backpointer to tile's PCI device */
> +	struct xe_device *xe;
> +
> +	/** @id: ID of the tile */
> +	u8 id;
> +
> +	/**
> +	 * @primary_gt: Primary GT
> +	 */
> +	struct xe_gt *primary_gt;
> +
> +	/**
> +	 * @media_gt: Media GT
> +	 *
> +	 * Only present on devices with media version >= 13.
> +	 */
> +	struct xe_gt *media_gt;
> +
> +	/**
> +	 * @mmio: MMIO info for a tile.
> +	 *
> +	 * Each tile has its own 16MB space in BAR0, laid out as:
> +	 * * 0-4MB: registers
> +	 * * 4MB-8MB: reserved
> +	 * * 8MB-16MB: global GTT
> +	 */
> +	struct xe_mmio mmio;
> +
> +	/** @mem: memory management info for tile */
> +	struct {
> +		/**
> +		 * @mem.vram: VRAM info for tile.
> +		 *
> +		 * Although VRAM is associated with a specific tile, it can
> +		 * still be accessed by all tiles' GTs.
> +		 */
> +		struct xe_vram_region vram;
> +
> +		/** @mem.ggtt: Global graphics translation table */
> +		struct xe_ggtt *ggtt;
> +
> +		/**
> +		 * @mem.kernel_bb_pool: Pool from which batchbuffers are allocated.
> +		 *
> +		 * Media GT shares a pool with its primary GT.
> +		 */
> +		struct xe_sa_manager *kernel_bb_pool;
> +	} mem;
> +
> +	/** @sriov: tile level virtualization data */
> +	union {
> +		struct {
> +			/** @sriov.pf.lmtt: Local Memory Translation Table. */
> +			struct xe_lmtt lmtt;
> +		} pf;
> +		struct {
> +			/** @sriov.vf.ggtt_balloon: GGTT regions excluded from use. */
> +			struct xe_ggtt_node *ggtt_balloon[2];
> +		} vf;
> +	} sriov;
> +
> +	/** @memirq: Memory Based Interrupts. */
> +	struct xe_memirq memirq;
> +
> +	/** @pcode: tile's PCODE */
> +	struct {
> +		/** @pcode.lock: protecting tile's PCODE mailbox data */
> +		struct mutex lock;
> +	} pcode;
> +
> +	/** @migrate: Migration helper for vram blits and clearing */
> +	struct xe_migrate *migrate;
> +
> +	/** @sysfs: sysfs' kobj used by xe_tile_sysfs */
> +	struct kobject *sysfs;
> +};
> +
> +#endif
> -- 
> 2.47.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation