✗ CI.checkpatch: warning for drm/i915/dmc: Deal with loss of pipe DMC state

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Deal with loss of pipe DMC state
URL   : https://patchwork.freedesktop.org/series/150112/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
202708c00696422fd217223bb679a353a5936e23
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit af3938a5a6a00326505fc3ce4c45b5637f9cfccc
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date:   Wed Jun 11 18:52:41 2025 +0300

    drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible
    
    On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
    and the main DMC does not restore any of it. This means the state will
    also be lost during PSR+DC5/6. It seems safest to not even enable the
    pipe DMC in that case (the main DMC does restore the pipe DMC enable
    bit in PIPEDMC_CONTROL_A for some reason).
    
    Since pipe DMC is only needed for "fast LACE" on these platforms we aren't
    actually losing anything here. In the future if we do want to enable
    "fast LACE" we'll just have to remember that it won't be compatible with
    PSR.
    
    Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+ /mt/dim checkpatch aafbd01c99cde1b0b8a117e0ae1b77e87554c7b6 drm-intel
4fa4a2f5b7b4 drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
5dc1d87f3cb7 drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS
9ba3cd5ddc52 drm/i915/dmc: Shuffle code around
-:112: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#112: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:590:
+		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));

total: 0 errors, 1 warnings, 0 checks, 162 lines checked
4ccacce51c14 drm/i915/dmc: Extract dmc_load_program()
9957880c2e83 drm/i915/dmc: Reload pipe DMC state on TGL when enabling pipe A
37ee5c5a5e91 drm/i915/dmc: Reload pipe DMC MMIO registers for pipe C/D on PTL+
7e59fe604c19 drm/i915/dmc: Assert DMC is loaded harder
b4c459e89c1a drm/i915/dmc: Pass crtc_state to intel_dmc_{enable, disable}_pipe()
af3938a5a6a0 drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible