✗ CI.checkpatch: warning for drm/i915/dmc: Deal with loss of pipe DMC state (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Deal with loss of pipe DMC state (rev2)
URL   : https://patchwork.freedesktop.org/series/150112/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
f8ff75ae1d2127635239b134695774ed4045d05b
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 816bc1b065c20f9fc847c463f7cc890608f23308
Author: Ville Syrjälä <ville.syrjala at linux.intel.com>
Date:   Tue Jun 17 20:07:59 2025 +0300

    drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible
    
    On TGL/derivatives the pipe DMC state is lost when PG1 is disabled,
    and the main DMC does not restore any of it. This means the state will
    also be lost during PSR+DC5/6. It seems safest to not even enable the
    pipe DMC in that case (the main DMC does restore the pipe DMC enable
    bit in PIPEDMC_CONTROL_A for some reason).
    
    Since pipe DMC is only needed for "fast LACE" on these platforms we aren't
    actually losing anything here. In the future if we do want to enable
    "fast LACE" we'll just have to remember that it won't be compatible with
    PSR.
    
    Reviewed-by: Uma Shankar <uma.shankar at intel.com>
    Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
+ /mt/dim checkpatch eb615557c4565c6236cd13b9cd164d472df1d0ed drm-intel
09f447df8dff drm/i915/dmc: Limit pipe DMC clock gating w/a to just ADL/DG2/MTL
7f2e73c1a08f drm/i915/dmc: Parametrize MTL_PIPEDMC_GATING_DIS
de217468fe50 drm/i915/dmc: Shuffle code around
-:112: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#112: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:590:
+		intel_de_write(display, PIPEDMC_INTERRUPT_MASK(pipe), ~pipedmc_interrupt_mask(display));

total: 0 errors, 1 warnings, 0 checks, 162 lines checked
6b4b47da30a6 drm/i915/dmc: Extract dmc_load_program()
42f14912309a drm/i915/dmc: Reload pipe DMC state on TGL when enabling pipe A
5cd0b03abe50 drm/i915/dmc: Reload pipe DMC MMIO registers for pipe C/D on various platforms
d77eba77ca3e drm/i915/dmc: Assert DMC is loaded harder
be6594e84dbc drm/i915/dmc: Pass crtc_state to intel_dmc_{enable, disable}_pipe()
816bc1b065c2 drm/i915/dmc: Do not enable the pipe DMC on TGL when PSR is possible