[PATCH v4 2/2] drm/xe/regs/xe_pmt: Macros for G-State and pcie link state residency offset

Cavitt, Jonathan jonathan.cavitt at intel.com
Tue Jun 17 21:14:26 UTC 2025


-----Original Message-----
From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Soham Purkait
Sent: Tuesday, June 17, 2025 10:16 AM
To: intel-xe at lists.freedesktop.org; Gupta, Anshuman <anshuman.gupta at intel.com>; Nilawar, Badal <badal.nilawar at intel.com>; Poosa, Karthik <karthik.poosa at intel.com>
Cc: De Marchi, Lucas <lucas.demarchi at intel.com>; Purkait, Soham <soham.purkait at intel.com>; Dixit, Ashutosh <ashutosh.dixit at intel.com>; Tauro, Riana <riana.tauro at intel.com>; Nikula, Jani <jani.nikula at intel.com>
Subject: [PATCH v4 2/2] drm/xe/regs/xe_pmt: Macros for G-State and pcie link state residency offset
> 
>    Add G-State residency and pcie link state residency
> offset macros for G2, G6, G8, G10, ModS and L0, L1, L1.2
> respectively.
> 
> v1 : Moved offset macros to drm/xe/regs/xe_pmt. (Riana)
> 
> Signed-off-by: Soham Purkait <soham.purkait at intel.com>

See my comments for patch 1.  Once you have swapped the order of the
two patches in this patch series, you can add my reviewed-by:
Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
-Jonathan Cavitt

> ---
>  drivers/gpu/drm/xe/regs/xe_pmt.h | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
> index b0efd9b48d1e..4e377b6eac92 100644
> --- a/drivers/gpu/drm/xe/regs/xe_pmt.h
> +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
> @@ -21,4 +21,14 @@
>  #define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
>  #define   SG_REMAP_BITS			REG_GENMASK(31, 24)
>  
> +#define BMG_G2_RESIDENCY_OFFSET			(0x530)
> +#define BMG_G6_RESIDENCY_OFFSET			(0x538)
> +#define BMG_G8_RESIDENCY_OFFSET			(0x540)
> +#define BMG_G10_RESIDENCY_OFFSET		(0x548)
> +#define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)
> +
> +#define PCIE_LINK_L0_RESIDENCY_COUNTER		(0x570)
> +#define PCIE_LINK_L1_RESIDENCY_COUNTER		(0x578)
> +#define PCIE_LINK_L1_2_RESIDENCY_COUNTER	(0x580)
> +
>  #endif
> -- 
> 2.34.1
> 
> 


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