[PATCH 5/5] drm/xe: disable wa_15015404425 for PTL B0

[Matt Atwood]

This workaround only applies to PTL Compute Die A0. However, this
information cannot be determined until after the GT is brought up. This
means that we will assume that it is required for the initial bring up of
the gt. After GT init, the oob workarounds are enabled for the GT. Use
this flag to then manually set the bit in the soc oob bit field to 0
which will help performance after device bring up.

Signed-off-by: Matt Atwood <matthew.s.atwood at intel.com>
---
 drivers/gpu/drm/xe/xe_pci.c        | 6 ++++++
 drivers/gpu/drm/xe/xe_wa_oob.rules | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index ded0f3dc8d73..a624c3fb9498 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -34,6 +34,9 @@
 #include "xe_tile.h"
 #include "xe_wa.h"
 
+#include "generated/xe_wa_oob.h"
+#include "generated/xe_soc_wa_oob.h"
+
 enum toggle_d3cold {
 	D3COLD_DISABLE,
 	D3COLD_ENABLE,
@@ -890,6 +893,9 @@ static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 	drm_dbg(&xe->drm, "d3cold: capable=%s\n",
 		str_yes_no(xe->d3cold.capable));
 
+	if (XE_WA(xe->tiles->media_gt, 15015404425_disable))
+		xe->oob[XE_SOC_WA_OOB_15015404425] = 0;
+
 	return 0;
 
 err_driver_cleanup:
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 8c2aa48cb33a..822cbff13819 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -71,3 +71,4 @@ no_media_l3	MEDIA_VERSION(3000)
 # primary GT GMDID
 14022085890	GRAPHICS_VERSION(2001)
 16026007364 	MEDIA_VERSION(3000)
+15015404425_disable	PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
-- 
2.49.0