[PATCH v6 1/2] drm/xe/regs/xe_pmt: Macros for G-State and pcie link state residency offset

[Poosa, Karthik]

On 25-06-2025 20:16, Cavitt, Jonathan wrote:
> -----Original Message-----
> From: Purkait, Soham <soham.purkait at intel.com>
> Sent: Wednesday, June 25, 2025 7:33 AM
> To: intel-xe at lists.freedesktop.org; Gupta, Anshuman <anshuman.gupta at intel.com>; Nilawar, Badal <badal.nilawar at intel.com>; Poosa, Karthik <karthik.poosa at intel.com>; Tauro, Riana <riana.tauro at intel.com>; Cavitt, Jonathan <jonathan.cavitt at intel.com>
> Cc: De Marchi, Lucas <lucas.demarchi at intel.com>; Purkait, Soham <soham.purkait at intel.com>; Dixit, Ashutosh <ashutosh.dixit at intel.com>; Nikula, Jani <jani.nikula at intel.com>
> Subject: [PATCH v6 1/2] drm/xe/regs/xe_pmt: Macros for G-State and pcie link state residency offset
>> Add G-State residency and pcie link state residency
>> offset macros for G2, G6, G8, G10, ModS and L0, L1, L1.2
>> respectively.
>>
>> v1:
>>   - Move offset macros to drm/xe/regs/xe_pmt. (Riana)
>> v6:
>>   - Mark MBG to pcie link residency offset. (Anshuman)
> s/MBG/BMG ?

Soham, you can also rephase this as -

Add BMG prefix to PCIe Link state residency counters macros names. (Anshman)

>
> But otherwise:
> Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
> -Jonathan Cavitt
>
>> Signed-off-by: Soham Purkait <soham.purkait at intel.com>
>> ---
>>   drivers/gpu/drm/xe/regs/xe_pmt.h | 10 ++++++++++
>>   1 file changed, 10 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
>> index b0efd9b48d1e..34f5bfdffe46 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_pmt.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
>> @@ -21,4 +21,14 @@
>>   #define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
>>   #define   SG_REMAP_BITS			REG_GENMASK(31, 24)
>>   
>> +#define BMG_G2_RESIDENCY_OFFSET			(0x530)
>> +#define BMG_G6_RESIDENCY_OFFSET			(0x538)
>> +#define BMG_G8_RESIDENCY_OFFSET			(0x540)
>> +#define BMG_G10_RESIDENCY_OFFSET		(0x548)
>> +#define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)
>> +
>> +#define BMG_PCIE_LINK_L0_RESIDENCY_OFFSET	(0x570)
>> +#define BMG_PCIE_LINK_L1_RESIDENCY_OFFSET	(0x578)
>> +#define BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET	(0x580)
>> +
>>   #endif
>> -- 
>> 2.34.1
>>
>>