[PATCH v8 1/2] drm/xe/regs/xe_pmt: Macros for G-State and pcie link state residency offset

[Lucas De Marchi]

On Mon, Jun 30, 2025 at 12:12:00PM +0530, Riana Tauro wrote:
>
>
>On 6/28/2025 12:30 AM, Soham Purkait wrote:
>>Add G-State residency and pcie link state residency
>>offset macros for G2, G6, G8, G10, ModS and L0, L1, L1.2
>>respectively.
>>
>>v1:
>>  - Move offset macros to drm/xe/regs/xe_pmt. (Riana)
>>v2:
>>  - Add BMG prefix to PCIe Link state residency
>>    offset macros names. (Anshman)
>>v3:
>>  - Rearrange residency offsets in ascending order. (Riana)
>>
>>Signed-off-by: Soham Purkait <soham.purkait at intel.com>
>>Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
>>Reviewed-by: Karthik Poosa <karthik.poosa at intel.com>
>
>Looks good to me
>Reviewed-by: Riana Tauro <riana.tauro at intel.com>

but please squash the macros in whatever patch they are used on. In xe
we usually don't add the registers unless there's a user and the most
straightforward to guarantee that is "include where it's used".

Lucas De Marchi

>
>>---
>>  drivers/gpu/drm/xe/regs/xe_pmt.h | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_pmt.h
>>index b0efd9b48d1e..038f34698206 100644
>>--- a/drivers/gpu/drm/xe/regs/xe_pmt.h
>>+++ b/drivers/gpu/drm/xe/regs/xe_pmt.h
>>@@ -21,4 +21,14 @@
>>  #define SG_REMAP_INDEX1			XE_REG(SOC_BASE + 0x08)
>>  #define   SG_REMAP_BITS			REG_GENMASK(31, 24)
>>+#define BMG_MODS_RESIDENCY_OFFSET		(0x4D0)
>>+#define BMG_G2_RESIDENCY_OFFSET			(0x530)
>>+#define BMG_G6_RESIDENCY_OFFSET			(0x538)
>>+#define BMG_G8_RESIDENCY_OFFSET			(0x540)
>>+#define BMG_G10_RESIDENCY_OFFSET		(0x548)
>>+
>>+#define BMG_PCIE_LINK_L0_RESIDENCY_OFFSET	(0x570)
>>+#define BMG_PCIE_LINK_L1_RESIDENCY_OFFSET	(0x578)
>>+#define BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET	(0x580)
>>+
>>  #endif
>