[PATCH 1/5] drm/xe: Add MI_LOAD_REGISTER_REG command definition

[Matt Roper]

On Mon, Mar 03, 2025 at 06:35:18PM +0100, Michal Wajdeczko wrote:
> The MI_LOAD_REGISTER_REG command reads value from a source register
> location and writes that value to a destination register location.
> 
> Bspec: 45730, 60233
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/instructions/xe_mi_commands.h | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> index 167fb0f742de..526bad9d4bac 100644
> --- a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> +++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> @@ -61,6 +61,10 @@
>  #define MI_LOAD_REGISTER_MEM		(__MI_INSTR(0x29) | XE_INSTR_NUM_DW(4))
>  #define   MI_LRM_USE_GGTT		REG_BIT(22)
>  
> +#define MI_LOAD_REGISTER_REG		(__MI_INSTR(0x2a) | XE_INSTR_NUM_DW(3))
> +#define   MI_LRR_DST_CS_MMIO		REG_BIT(19)
> +#define   MI_LRR_SRC_CS_MMIO		REG_BIT(18)
> +
>  #define MI_COPY_MEM_MEM			(__MI_INSTR(0x2e) | XE_INSTR_NUM_DW(5))
>  #define   MI_COPY_MEM_MEM_SRC_GGTT	REG_BIT(22)
>  #define   MI_COPY_MEM_MEM_DST_GGTT	REG_BIT(21)
> -- 
> 2.47.1
> 
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation