[PATCH 4/5] drm/xe/vf: Stop applying save-restore MMIOs if VF

[Matt Roper]

On Mon, Mar 03, 2025 at 12:09:50PM -0600, Lucas De Marchi wrote:
> On Mon, Mar 03, 2025 at 06:35:21PM +0100, Michal Wajdeczko wrote:
> > Currently we are blocking processing of all save-restore rules
> > by the VFs inside the xe_rtp_process_to_sr() function, but we
> > want to unblock that to allow processing of the LRC WA rules.
> > 
> > To avoid hitting WARNs about reading an inaccessible registers by
> > the VFs, stop applying save-restore MMIOs action if VF, without
> > relying that SR list will be always empty for the VF.
> > 
> > Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_reg_sr.c | 3 +++
> > 1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
> > index 9475e3f74958..fc8447a838c4 100644
> > --- a/drivers/gpu/drm/xe/xe_reg_sr.c
> > +++ b/drivers/gpu/drm/xe/xe_reg_sr.c
> > @@ -173,6 +173,9 @@ void xe_reg_sr_apply_mmio(struct xe_reg_sr *sr, struct xe_gt *gt)
> 
> couldn't we simply have a a generic xe_reg_sr_apply_gpu_job()?

Setting up batch submission at the points we're doing these MMIO writes
seems pretty complicated/awkward.  Also, depending on exactly the
workarounds are trying to do, it might be important to get these non-LRC
registers set before any batch submissions happen.  And even if we did
do batchbuffer writes to these registers it still wouldn't change the
SRIOV situation --- there's only a single global copy of these registers
in hardware, and that copy is managed by the PF, so the VF
can't/shouldn't be trying to touch it.

The LRC workarounds truly are a different beast where we're just cooking
an image up front that will later get restored on context switches
(independent of PF or VF status).


Matt

> 
> If we still need to filter registers, we could probably add tags to the
> xa storage... ?
> 
> Lucas De Marchi

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation