✓ CI.checkpatch: success for drm/i915/dsi: let HW maintain the HS-TRAIL timing

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: let HW maintain the HS-TRAIL timing
URL   : https://patchwork.freedesktop.org/series/146128/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
cbb4e4a079d89106c2736adc3c7de6f9dc56da07
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 5acafa97718bf28924e9c973360663a196fa3f95
Author: William Tseng <william.tseng at intel.com>
Date:   Tue Mar 11 18:06:26 2025 +0800

    drm/i915/dsi: let HW maintain the HS-TRAIL timing
    
    This change is to avoid over-specification of the TEOT timing
    parameter, which is derived from software in current design.
    
    Supposed that THS-TRAIL and THS-EXIT have the minimum values,
    i.e., 60 and 100 in ns. If SW is overriding the HW default,
    the TEOT value becomes 150 ns, approximately calculated by
    the following formula.
    
      DIV_ROUND_UP(60/50)*50 + DIV_ROUND_UP(100/50))*50/2, where 50
      is LP Escape Clock time in ns.
    
    The TEOT value 150 ns is larger than the maximum value,
    around 136 ns if UI is 1.8ns, (105 ns + 12*UI, defined by MIPI
    DPHY specification).
    
    However, the TEOT value will meet the specification if THS-TRAIL
    is set to the HW default, instead of software overriding.
    
    The timing change is made for both data lane and clock lane.
    
    v1: initial version.
    v2: change clock lane dphy timings.
    v3: remove calculation of trail cnt.
    v4: rebase.
    
    Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13891
    Cc: Ville Syrjala <ville.syrjala at linux.intel.com>
    Cc: Jani Nikula <jani.nikula at linux.intel.com>
    Cc: Vandita Kulkarni <vandita.kulkarni at intel.com>
    Cc: Lee Shawn C <shawn.c.lee at intel.com>
    Cc: Cooper Chiou <cooper.chiou at intel.com>
    Signed-off-by: William Tseng <william.tseng at intel.com>
    Acked-by: Vandita Kulkarni <vandita.kulkarni at intel.com>
+ /mt/dim checkpatch 777e1850811f9864aa8b55940634d3da19712bf7 drm-intel
5acafa97718b drm/i915/dsi: let HW maintain the HS-TRAIL timing