[PATCH v3 0/8] AuxCCS handling and render compression modifiers

[Juha-Pekka Heikkilä]

Hi Tvrtko,

I did quick run with these patches. With these changes on top of
today's drm-tip I got a complete system freeze on mtl and its variants
when do modprobe. I had kgdb enabled but I wasn't even thrown there,
the machine went completely unresponsive. On 3/3 tries modprobe xe
always completely froze the box.

/Juha-Pekka


On Tue, Mar 18, 2025 at 6:22 PM Tvrtko Ursulin
<tvrtko.ursulin at igalia.com> wrote:
>
> A series to fix and add xe support for AuxCSS framebuffers via DPT.
>
> Currently the auxiliary buffer data isn't mapped into the page tables at all so
> cf48bddd31de ("drm/i915/display: Disable AuxCCS framebuffers if built for Xe")
> had to disable the support.
>
> On top of that there are missing flushes and invalidations both from the ring
> buffer side and from the CPU side.
>
> Tested with KDE Wayland, on Lenovo Carbon X1 ADL-P:
>
>   [PLANE:32:plane 1A]: type=PRI
>           uapi: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=visible, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
>           hw: [FB:242] AR30 little-endian (0x30335241),0x100000000000008,2880x1800, visible=yes, src=2880.000000x1800.000000+0.000000+0.000000, dst=2880x1800+0+0, rotation=0 (0x00000001)
>
> Display seems working fine - no artefacts, no DMAR/PIPE faults. CI also appears
> to be happy with v2.
>
> v2:
>  * More patches added to fix kms_flip_tiling.
>
> v3:
>  * Rebased after some cleanup patches from v2 were merged.
>  * Added people to Cc as suggested by Rodrigo.
>  * Adjusted last patch title. (Rodrigo)
>  * Apply GGTT flushing only to iomapped system memory buffers.
>
> Cc: José Roberto de Souza <jose.souza at intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> Cc: Michael J. Ruhl <michael.j.ruhl at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> Tvrtko Ursulin (8):
>   drm/xe: Add ring buffer handling for AuxCCS
>   drm/xe: Use fb cached min alignment
>   drm/xe: Reduce DPT table alignment as in i915
>   drm/xe: Flush GGTT writes after populating DPT
>   drm/xe: Handle DPT in system memory
>   drm/xe: Force flush system memory AuxCCS framebuffers before scan out
>   drm/xe/display: Add support for AuxCCS
>   drm/i915/display: Expose AuxCCS frame buffer modifiers for Xe
>
>  .../drm/i915/display/skl_universal_plane.c    |   6 -
>  drivers/gpu/drm/xe/display/xe_fb_pin.c        | 181 ++++++++++++++----
>  .../gpu/drm/xe/instructions/xe_gpu_commands.h |   1 +
>  .../gpu/drm/xe/instructions/xe_mi_commands.h  |   6 +
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h          |   1 +
>  drivers/gpu/drm/xe/xe_bo_types.h              |  14 +-
>  drivers/gpu/drm/xe/xe_ring_ops.c              | 173 +++++++++--------
>  drivers/gpu/drm/xe/xe_ring_ops_types.h        |   2 +-
>  8 files changed, 261 insertions(+), 123 deletions(-)
>
> --
> 2.48.0
>