[PATCH] drm/xe/xe2hpg: Add Wa_16025250150

[Upadhyay, Tejas]

> -----Original Message-----
> From: Bhatia, Aradhya <aradhya.bhatia at intel.com>
> Sent: Tuesday, March 25, 2025 12:15 PM
> To: Roper, Matthew D <matthew.d.roper at intel.com>
> Cc: Intel XE List <intel-xe at lists.freedesktop.org>; Siddiqui, Ayaz A
> <ayaz.siddiqui at intel.com>; Upadhyay, Tejas <tejas.upadhyay at intel.com>;
> Ghimiray, Himal Prasad <himal.prasad.ghimiray at intel.com>; Bhatia, Aradhya
> <aradhya.bhatia at intel.com>
> Subject: [PATCH] drm/xe/xe2hpg: Add Wa_16025250150
> 
> Add Wa_16025250150 for the Xe2_HPG (graphics version: 20.01) platforms.
> It is a permanent workaround, and applicable on all the steppings.
> 
> Signed-off-by: Aradhya Bhatia <aradhya.bhatia at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 12 ++++++++++++
>  drivers/gpu/drm/xe/xe_wa.c           | 12 ++++++++++++
>  2 files changed, 24 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index da1f198ac107..5c1946f92e0c 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -392,6 +392,18 @@
>  #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
>  #define   XEHP_LNESPARE				REG_BIT(19)
> 
> +#define LSN_VC_REG2				XE_REG(0xb0c8)

This looks to be MCR reg so use XE_REG_MCR

> +#define   LSN_LNI_WGT_MASK			REG_GENMASK(31,
> 28)
> +#define   LSN_LNI_WGT(value)
> 	REG_FIELD_PREP(LSN_LNI_WGT_MASK, value)
> +#define   LSN_LNE_WGT_MASK			REG_GENMASK(27,
> 24)
> +#define   LSN_LNE_WGT(value)
> 	REG_FIELD_PREP(LSN_LNE_WGT_MASK, value)
> +#define   LSN_DIM_X_WGT_MASK			REG_GENMASK(23,
> 20)
> +#define   LSN_DIM_X_WGT(value)
> 	REG_FIELD_PREP(LSN_DIM_X_WGT_MASK, value)
> +#define   LSN_DIM_Y_WGT_MASK			REG_GENMASK(19,
> 16)
> +#define   LSN_DIM_Y_WGT(value)
> 	REG_FIELD_PREP(LSN_DIM_Y_WGT_MASK, value)
> +#define   LSN_DIM_Z_WGT_MASK			REG_GENMASK(15,
> 12)
> +#define   LSN_DIM_Z_WGT(value)
> 	REG_FIELD_PREP(LSN_DIM_Z_WGT_MASK, value)
> +
>  #define L3SQCREG2				XE_REG_MCR(0xb104)
>  #define   COMPMEMRD256BOVRFETCHEN		REG_BIT(20)
> 
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index
> 24f644c0a673..6f6563cc7430 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -230,6 +230,18 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
> 
> +	/* Xe2_HPG */
> +
> +	{ XE_RTP_NAME("16025250150"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2001)),
> +	  XE_RTP_ACTIONS(SET(LSN_VC_REG2,
> +			     LSN_LNI_WGT(1) |
> +			     LSN_LNE_WGT(1) |
> +			     LSN_DIM_X_WGT(1) |
> +			     LSN_DIM_Y_WGT(1) |
> +			     LSN_DIM_Z_WGT(1)))
> +	},
> +

Apart from above comment,
Reviewed-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

>  	/* Xe2_HPM */
> 
>  	{ XE_RTP_NAME("16021867713"),
> 
> base-commit: 9a42bdcde0f77b2c1e947e283cc3b267b1ce2056
> --
> 2.34.1