✓ CI.checkpatch: success for drm/xe: Make PPHWSP size explicit in xe_gt_lrc_size()

[Patchwork]

== Series Details ==

Series: drm/xe: Make PPHWSP size explicit in xe_gt_lrc_size()
URL   : https://patchwork.freedesktop.org/series/146970/
State : success

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99e5a866b5e13f134e606a3e29d9508d97826fb3
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit b443fe8b96c4117cb37ef512669d3e3c62d10b82
Author: Gustavo Sousa <gustavo.sousa at intel.com>
Date:   Fri Mar 28 13:50:50 2025 -0300

    drm/xe: Make PPHWSP size explicit in xe_gt_lrc_size()
    
    The context of each engine starts with a 4k scratch memory space for the
    "Per-process HW status page" (PPHWSP). In xe_gt_lrc_size(), we have been
    implicitly accounting for that page in the switch statement on the
    engine class.
    
    Since the PPHWSP is common to all engines, let's extract that into it's
    own assignment. That makes the context structure more explicit in the
    code and aligns better with the descriptions in Bspec.
    
    Another advantage of keeping it separate is that now the sizes used in
    the switch statement match the sizes we calculate engine-specific
    context images, which have their own Bspec pages.
    
    Bspec: 67296, 60159, 45554
    Signed-off-by: Gustavo Sousa <gustavo.sousa at intel.com>
+ /mt/dim checkpatch 2e2d39cb4f3dd3465c7bca7b8f2290570e85aa1b drm-intel
b443fe8b96c4 drm/xe: Make PPHWSP size explicit in xe_gt_lrc_size()