✗ CI.checkpatch: warning for drm/i915/display: implement wa_18038517565 (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/display: implement wa_18038517565 (rev3)
URL   : https://patchwork.freedesktop.org/series/144183/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
99e5a866b5e13f134e606a3e29d9508d97826fb3
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 8de346ee09711c6273a8fbc239d7faedf3069b0c
Author: Vinod Govindapillai <vinod.govindapillai at intel.com>
Date:   Sun Mar 30 20:26:16 2025 +0300

    drm/i915/display: implement wa_18038517565
    
    Disable FBC compressor clock gating before enabling FBC and
    clear it after disabling FBC.
    
    v2: update the DG2 registers for this wa
    
    v3: use local variable and single line reg definition (Jani)
    
    Bspec: 74212, 72197, 69741, 65555
    Signed-off-by: Vinod Govindapillai <vinod.govindapillai at intel.com>
+ /mt/dim checkpatch e5666096aca27527596cf05ff22425f56e40dd40 drm-intel
8de346ee0971 drm/i915/display: implement wa_18038517565
-:81: WARNING:LONG_LINE: line length of 116 exceeds 100 columns
#81: FILE: drivers/gpu/drm/i915/i915_reg.h:4248:
+#define MTL_PIPE_CLKGATE_DIS2(pipe)		_MMIO_PIPE(pipe, _MTL_PIPE_CLKGATE_DIS2_A, _MTL_PIPE_CLKGATE_DIS2_B)

total: 0 errors, 1 warnings, 0 checks, 58 lines checked