<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> </head> <body> <div dir="auto">Please ignore this. </div> <div dir="auto">Will resent with fixing the Subject. </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg" dir="ltr">From: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com> Sent: Wednesday, October 18, 2023 8:18:28 AM To: intel-xe@lists.freedesktop.org <intel-xe@lists.freedesktop.org> Cc: Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com> Subject: [PATCH v8 00/10] *Supporting RAS on XE <div> </div> </div> <div class="BodyFragment"> <div class="PlainText">Our platforms support Reliability, Availability and Serviceability(RAS). In case of hardware errors, our hardwares provides the causes via sending interrupt or pcie errors. The fatal errors are propogated as pci errors and non fatal errors as MSI. This series focuses on loging and updating counters for these errors, which will be helpful to avoid, detect and repair hardware faults. This [1] series proposes mechanism to expose this counters to userspace. [1]: <a href="https://patchwork.freedesktop.org/series/118435/">https://patchwork.freedesktop.org/series/118435/</a> The error counters exposed by KMD will be used by L0/sysman They will be categorized to specific category of error in sysman: <a href="https://spec.oneapi.io/level-zero/latest/sysman/api.html#ras">https://spec.oneapi.io/level-zero/latest/sysman/api.html#ras</a> We have very limited capabilities for error injection to validate the code flow. Output of L3 fabric fatal injection from PVC is: xe 0000:8c:00.0: [drm] *ERROR* [Hardware Error]: TILE0 detected GT FATAL error bit[0] is set xe 0000:8c:00.0: [drm] *ERROR* [Hardware Error]: GT0 detected L3 FABRIC FATAL error. ERR_VECT_GT_FATAL[7]:0x00000087 v2 - Use different headers for error registers. (Nikula) - Correctable errors shouldn't be considered as dmesg errors (Matt) - Limit series to HW errors.(Aravind) v3 - Rebase v4 - Use xe_regs.h only for registers, move enums out of it. - Make sure global data/structures are immutable. - Avoid adding custom error logging macro's. - Redesign the registers error name and counter index structures for maintainability. (Nikula) v5 - move struct hw_err_regs out of CONFIG_DRM_XE_DISPLAY. v6 - Addressing Review comments from Aravind. v7 - CI fixes. v8 - Conditional check fixes. Himal Prasad Ghimiray (4): drm/xe: Handle errors from various components. drm/xe: Log and count the GT hardware errors. drm/xe: Support GT hardware error reporting for PVC. drm/xe: Support GSC hardware error reporting for PVC. drm/xe: Notify userspace about GSC HW errors. drm/xe: Support SOC FATAL error handling for PVC. drm/xe: Support SOC NONFATAL error handling for PVC. drm/xe: Handle MDFI error severity. drm/xe: Clear SOC CORRECTABLE error registers. drm/xe: Clear all SoC errors post warm reset. drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/regs/xe_gt_error_regs.h | 29 + drivers/gpu/drm/xe/regs/xe_regs.h | 5 +- drivers/gpu/drm/xe/regs/xe_tile_error_regs.h | 65 ++ drivers/gpu/drm/xe/xe_device.c | 14 + drivers/gpu/drm/xe/xe_device_types.h | 21 + drivers/gpu/drm/xe/xe_gt.c | 1 + drivers/gpu/drm/xe/xe_gt_types.h | 7 + drivers/gpu/drm/xe/xe_hw_error.c | 919 +++++++++++++++++++ drivers/gpu/drm/xe/xe_hw_error.h | 210 +++++ drivers/gpu/drm/xe/xe_irq.c | 9 + drivers/gpu/drm/xe/xe_tile.c | 1 + include/uapi/drm/xe_drm.h | 8 + 13 files changed, 1289 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/xe/regs/xe_gt_error_regs.h create mode 100644 drivers/gpu/drm/xe/regs/xe_tile_error_regs.h create mode 100644 drivers/gpu/drm/xe/xe_hw_error.c create mode 100644 drivers/gpu/drm/xe/xe_hw_error.h -- 2.25.1 </div> </div> </body> </html>