<!DOCTYPE html><html><head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> </head> <body> <p><br> </p> <div class="moz-cite-prefix">On 25-06-2025 20:16, Cavitt, Jonathan wrote:<br> </div> <blockquote type="cite" cite="mid:CH0PR11MB5444E60E76CB4BAFE1CF0CDBE57BA@CH0PR11MB5444.namprd11.prod.outlook.com"> <pre wrap="" class="moz-quote-pre">-----Original Message----- From: Purkait, Soham <a class="moz-txt-link-rfc2396E" href="mailto:soham.purkait@intel.com"><soham.purkait@intel.com></a> Sent: Wednesday, June 25, 2025 7:33 AM To: <a class="moz-txt-link-abbreviated" href="mailto:intel-xe@lists.freedesktop.org">intel-xe@lists.freedesktop.org</a>; Gupta, Anshuman <a class="moz-txt-link-rfc2396E" href="mailto:anshuman.gupta@intel.com"><anshuman.gupta@intel.com></a>; Nilawar, Badal <a class="moz-txt-link-rfc2396E" href="mailto:badal.nilawar@intel.com"><badal.nilawar@intel.com></a>; Poosa, Karthik <a class="moz-txt-link-rfc2396E" href="mailto:karthik.poosa@intel.com"><karthik.poosa@intel.com></a>; Tauro, Riana <a class="moz-txt-link-rfc2396E" href="mailto:riana.tauro@intel.com"><riana.tauro@intel.com></a>; Cavitt, Jonathan <a class="moz-txt-link-rfc2396E" href="mailto:jonathan.cavitt@intel.com"><jonathan.cavitt@intel.com></a> Cc: De Marchi, Lucas <a class="moz-txt-link-rfc2396E" href="mailto:lucas.demarchi@intel.com"><lucas.demarchi@intel.com></a>; Purkait, Soham <a class="moz-txt-link-rfc2396E" href="mailto:soham.purkait@intel.com"><soham.purkait@intel.com></a>; Dixit, Ashutosh <a class="moz-txt-link-rfc2396E" href="mailto:ashutosh.dixit@intel.com"><ashutosh.dixit@intel.com></a>; Nikula, Jani <a class="moz-txt-link-rfc2396E" href="mailto:jani.nikula@intel.com"><jani.nikula@intel.com></a> Subject: [PATCH v6 2/2] drm/xe/xe_debugfs: Exposure of G-State and pcie link state residency counters through debugfs </pre> <blockquote type="cite"> <pre wrap="" class="moz-quote-pre"> Add debug nodes, "dgfx_pkg_residencies" for G-states (G2, G6, G8, G10, ModS) and "dgfx_pcie_link_residencies" for PCIe link states(L0, L1, L1.2) residency counters. v1: - Expose all G-State residency counter values under dgfx_pkg_residencies. (Anshuman) - Include runtime_get/put. (Riana) v2: - Move "dgfx_pkg_residencies" from "gtidle". (Anshuman) v3: - Include debugfs node "dgfx_pcie_link_residencies" for pcie link residency counter values. (Anshuman) v4: - Include check for BMG for and add helper function for repetitive code. (Riana) - Use "drm_debugfs_create_files" to create debugfs. (Karthik) v5: - Reorder commits to reflect the correct dependency hierarchy. (Jonathan) - Simplification of commit message and rectified register offset.(Karthik) - Error handling and return before printing. (Riana) v6: - Remove check for DGFX as BMG is discrete. (Karthik) Signed-off-by: Soham Purkait <a class="moz-txt-link-rfc2396E" href="mailto:soham.purkait@intel.com"><soham.purkait@intel.com></a> </pre> </blockquote> <pre wrap="" class="moz-quote-pre"> LGTM. Reviewed-by: Jonathan Cavitt <a class="moz-txt-link-rfc2396E" href="mailto:jonathan.cavitt@intel.com"><jonathan.cavitt@intel.com></a> -Jonathan Cavitt </pre> <blockquote type="cite"> <pre wrap="" class="moz-quote-pre">--- drivers/gpu/drm/xe/xe_debugfs.c | 71 +++++++++++++++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c index d83cd6ed3fa8..3f276d85c2ba 100644 --- a/drivers/gpu/drm/xe/xe_debugfs.c +++ b/drivers/gpu/drm/xe/xe_debugfs.c @@ -11,16 +11,19 @@ #include <drm/drm_debugfs.h> +#include "regs/xe_pmt.h" #include "xe_bo.h" #include "xe_device.h" #include "xe_force_wake.h" #include "xe_gt_debugfs.h" #include "xe_gt_printk.h" #include "xe_guc_ads.h" +#include "xe_mmio.h" #include "xe_pm.h" #include "xe_pxp_debugfs.h" #include "xe_sriov.h" #include "xe_step.h" +#include "xe_vsec.h" #ifdef CONFIG_DRM_XE_DEBUG #include "xe_bo_evict.h" @@ -30,6 +33,23 @@ DECLARE_FAULT_ATTR(gt_reset_failure); +static void read_residency_counter(struct xe_device *xe, struct xe_mmio *mmio, + u32 offset, char *name, struct drm_printer *p) +{ + u64 residency = 0; + int ret; + + ret = xe_pmt_telem_read(to_pci_dev(xe->drm.dev), + xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID), + &residency, offset, sizeof(residency)); + if (ret != sizeof(residency)) { + drm_warn(&xe->drm, "%s counter failed to read, ret %d\n", name, ret); + return; + } + + drm_printf(p, "%s : %llu\n", name, residency); +} + static struct xe_device *node_to_xe(struct drm_info_node *node) { return to_xe_device(node->minor->dev); @@ -82,11 +102,57 @@ static int sriov_info(struct seq_file *m, void *data) return 0; } +static int dgfx_pkg_residencies_show(struct seq_file *m, void *data) +{ + struct xe_device *xe; + struct xe_mmio *mmio; + struct drm_printer p; + + xe = node_to_xe(m->private); + p = drm_seq_file_printer(m); + xe_pm_runtime_get(xe); + mmio = xe_root_tile_mmio(xe); + + read_residency_counter(xe, mmio, BMG_G2_RESIDENCY_OFFSET, "Package G2", &p); + read_residency_counter(xe, mmio, BMG_G6_RESIDENCY_OFFSET, "Package G6", &p); + read_residency_counter(xe, mmio, BMG_G8_RESIDENCY_OFFSET, "Package G8", &p); + read_residency_counter(xe, mmio, BMG_G10_RESIDENCY_OFFSET, "Package G10", &p); + read_residency_counter(xe, mmio, BMG_MODS_RESIDENCY_OFFSET, "Package ModS", &p); + xe_pm_runtime_put(xe); + return 0; +} + +static int dgfx_pcie_link_residencies_show(struct seq_file *m, void *data) +{ + struct xe_device *xe; + struct xe_mmio *mmio; + struct drm_printer p; + + xe = node_to_xe(m->private); + p = drm_seq_file_printer(m); + xe_pm_runtime_get(xe); + mmio = xe_root_tile_mmio(xe); + + read_residency_counter(xe, mmio, BMG_PCIE_LINK_L0_RESIDENCY_OFFSET, + "PCIE LINK L0 RESIDENCY", &p); + read_residency_counter(xe, mmio, BMG_PCIE_LINK_L1_RESIDENCY_OFFSET, + "PCIE LINK L1 RESIDENCY", &p); + read_residency_counter(xe, mmio, BMG_PCIE_LINK_L1_2_RESIDENCY_OFFSET, + "PCIE LINK L1.2 RESIDENCY", &p); + xe_pm_runtime_put(xe); + return 0; +} + static const struct drm_info_list debugfs_list[] = { {"info", info, 0}, { .name = "sriov_info", .show = sriov_info, }, }; +static const struct drm_info_list debugfs_residencies[] = { + { .name = "dgfx_pkg_residencies", .show = dgfx_pkg_residencies_show, }, + { .name = "dgfx_pcie_link_residencies", .show = dgfx_pcie_link_residencies_show, }, +}; + static int forcewake_open(struct inode *inode, struct file *file) { struct xe_device *xe = inode->i_private; @@ -240,6 +306,11 @@ void xe_debugfs_register(struct xe_device *xe) ARRAY_SIZE(debugfs_list), root, minor); + if (xe->info.platform == XE_BATTLEMAGE) + drm_debugfs_create_files(debugfs_residencies, + ARRAY_SIZE(debugfs_residencies), + root, minor); + debugfs_create_file("forcewake_all", 0400, root, xe, &forcewake_all_fops); -- 2.34.1 </pre> </blockquote> </blockquote>  <p class="MsoPlainText">LGTM.</p> <p class="MsoPlainText">Reviewed-by: Karthik Poosa <<a href="mailto:karthik.poosa@intel.com" class="moz-txt-link-freetext">karthik.poosa@intel.com</a>></p> <br> <blockquote type="cite" cite="mid:CH0PR11MB5444E60E76CB4BAFE1CF0CDBE57BA@CH0PR11MB5444.namprd11.prod.outlook.com"> <blockquote type="cite"> <pre wrap="" class="moz-quote-pre"> </pre> </blockquote> </blockquote> </body> </html>