[Libdlo] libdlo dynamic modeset

[Andy Fisher]

The use of LFSRs may seem "counter" intuitive (sorry I couldn't resist  
the pun) but as has been stated on the list LFSRs are generally faster  
than an equivalent length binary counter.

When DislayLink (or Newnham Research as it was back then) first got  
off the ground early proof of concept designs used FPGAs. In fact some  
of the early products were FPGA based. Getting FPGAs of this vintage  
to run at speeds sufficient for rastering video was challenging so  
creative thinking had to be applied in a number of places!

Generally an an optimal length LFSR counts around all the possible  
binary values (except zero) in a totally predictable, if not  
particularly intuitive, sequence. The important thing in our case is  
that the critical feedback path only cascades through a small number  
of XOR gates. In a binary counter the feedback runs the whole length
of the counter, through 15 xor gates in our case. An additional  
benefit in the FPGA case was that the 4 input XOR gate required for  
the 16 bit LFSR mapped perfectly to one lookup table in the FPGA of  
choice resulting in a
very fast counter. At the start of each line (or frame for vertical  
timing) the counter is initialised to all ones and comparators trigger  
events such as start and end of sync pulses.

These days in our ASICs these techniques are not really necessary to  
achieve the speeds required and it is very likely that our future  
devices will not work this way.

One of the aims of libdlo is to provide a library with a consistent  
interface across our developing range of devices to unify changes like  
this one and others (of considerably higher complexity) without each  
application having to continuously modify their code. It is obviously  
going to need to evolve and the useful feedback from this list is  
steering the work we are trying to get done updating the library.

Andy Fisher

(DisplayLink Ltd)