[Libreoffice-commits] core.git: writerfilter/qa writerfilter/source
Caolán McNamara
caolanm at redhat.com
Tue Apr 22 09:24:36 PDT 2014
writerfilter/qa/cppunittests/rtftok/data/pass/TCI-TN65GP-DDRHDLL-partial.rtf | 1719 ++++++++++
writerfilter/source/dmapper/NumberingManager.cxx | 5
writerfilter/source/rtftok/rtfsdrimport.cxx | 48
3 files changed, 1759 insertions(+), 13 deletions(-)
New commits:
commit 5aeaba2e6592dab0404301dcef644144f82ffcbf
Author: Caolán McNamara <caolanm at redhat.com>
Date: Tue Apr 22 17:23:26 2014 +0100
Resolves: rhbz#1089377 crash on loading a specific rtf
Change-Id: I26864f3a2247f5d7184f395cfed91eaf92e36295
diff --git a/writerfilter/qa/cppunittests/rtftok/data/pass/TCI-TN65GP-DDRHDLL-partial.rtf b/writerfilter/qa/cppunittests/rtftok/data/pass/TCI-TN65GP-DDRHDLL-partial.rtf
new file mode 100644
index 0000000..7cdb1e1
--- /dev/null
+++ b/writerfilter/qa/cppunittests/rtftok/data/pass/TCI-TN65GP-DDRHDLL-partial.rtf
@@ -0,0 +1,1719 @@
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+\par }}}}
+{\shp{\*\shpinst\shpleft1281\shptop3312\shpright4428\shpbottom9000\shpfhdr0\shpbxcolumn\shpbxignore\shpbypara\shpbyignore\shpwr3\shpwrk0\shpfblwtxt0\shpz2\shplid1030{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}
+{\sp{\sn lTxid}{\sv 327680}}{\sp{\sn dxTextLeft}{\sv 64008}}{\sp{\sn dyTextTop}{\sv 182880}}{\sp{\sn dxTextRight}{\sv 137160}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1030}}
+{\sp{\sn fFitShapeToText}{\sv 0}}{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fLine}{\sv 0}}{\sp{\sn lidRegroup}{\sv 1}}{\sp{\sn posrelh}{\sv 0}}{\sp{\sn posrelv}{\sv 0}}{\sp{\sn fLayoutInCell}{\sv 1}}{\sp{\sn fLayoutInCell}{\sv 1}}{\shptxt \ltrpar
+\pard\plain \ltrpar\s21\ql \li50\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin50\itap0 \rtlch \ab\af1\afs22\alang1025 \ltrch \b\scaps\f1\fs22\expnd3\expndtw17\cf1\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch
+\insrsid7564464 Features
+\par }\pard\plain \ltrpar\qr \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs16\alang1025 \ltrch \f1\fs16\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+\par {\listtext\pard\plain\ltrpar \s22 \rtlch \af46\afs18 \ltrch \f46\fs18\cf17\lang1024\langfe1024\noproof \loch\af46\dbch\af0\hich\f46 \'34\tab}}\pard\plain \ltrpar\s22\ql \fi-216\li216\ri0\widctlpar
+\tqr\tx216\aspalpha\aspnum\faauto\ls38\adjustright\rin0\lin216\itap0 \rtlch \af1\afs19\alang1025 \ltrch \f1\fs19\cf17\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464 Designed for high-speed DDR style interface applications.
+\par }\pard\plain \ltrpar\qr \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs16\alang1025 \ltrch \f1\fs16\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+\par {\listtext\pard\plain\ltrpar \s22 \rtlch \af46\afs18 \ltrch \f46\fs18\cf17\lang1024\langfe1024\noproof \loch\af46\dbch\af0\hich\f46 \'34\tab}}\pard\plain \ltrpar\s22\ql \fi-216\li216\ri0\widctlpar
+\tqr\tx216\aspalpha\aspnum\faauto\ls38\adjustright\rin0\lin216\itap0 \rtlch \af1\afs19\alang1025 \ltrch \f1\fs19\cf17\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464 Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
+\par }\pard\plain \ltrpar\qr \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs16\alang1025 \ltrch \f1\fs16\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+\par {\listtext\pard\plain\ltrpar \s22 \rtlch \af46\afs18 \ltrch \f46\fs18\cf17\lang1024\langfe1024\noproof \loch\af46\dbch\af0\hich\f46 \'34\tab}}\pard\plain \ltrpar\s22\ql \fi-216\li216\ri0\widctlpar
+\tqr\tx216\aspalpha\aspnum\faauto\ls38\adjustright\rin0\lin216\itap0 \rtlch \af1\afs19\alang1025 \ltrch \f1\fs19\cf17\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464 Delays multiple periodic or aperiodic signals independent of voltage and temperature.
+\par }\pard\plain \ltrpar\qr \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs16\alang1025 \ltrch \f1\fs16\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+\par {\listtext\pard\plain\ltrpar \s22 \rtlch \af46\afs18 \ltrch \f46\fs18\cf17\lang1024\langfe1024\noproof \loch\af46\dbch\af0\hich\f46 \'34\tab}}\pard\plain \ltrpar\s22\ql \fi-216\li216\ri0\widctlpar
+\tqr\tx216\aspalpha\aspnum\faauto\ls38\adjustright\rin0\lin216\itap0 \rtlch \af1\afs19\alang1025 \ltrch \f1\fs19\cf17\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464 Delivers optimal jitter \line performance over a wide \line frequency range.
+\par }\pard\plain \ltrpar\qr \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs16\alang1025 \ltrch \f1\fs16\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+\par {\listtext\pard\plain\ltrpar \s22 \rtlch \af46\afs18 \ltrch \f46\fs18\cf17\lang1024\langfe1024\noproof \loch\af46\dbch\af0\hich\f46 \'34\tab}}\pard\plain \ltrpar\s22\ql \fi-216\li216\ri0\widctlpar
+\tqr\tx216\aspalpha\aspnum\faauto\ls38\adjustright\rin0\lin216\itap0 \rtlch \af1\afs19\alang1025 \ltrch \f1\fs19\cf17\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464 Available in flexible form factors for easier integration.
+\par }}}}
+{\shp{\*\shpinst\shpleft5061\shptop3312\shpright11541\shpbottom11952\shpfhdr0\shpbxcolumn\shpbxignore\shpbypara\shpbyignore\shpwr3\shpwrk0\shpfblwtxt0\shpz1\shplid1031{\sp{\sn shapeType}{\sv 202}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}
+{\sp{\sn lTxid}{\sv 393216}}{\sp{\sn dxTextLeft}{\sv 274320}}{\sp{\sn dyTextTop}{\sv 182880}}{\sp{\sn dxTextRight}{\sv 137160}}{\sp{\sn dyTextBottom}{\sv 0}}{\sp{\sn hspNext}{\sv 1031}}
+{\sp{\sn fFilled}{\sv 0}}{\sp{\sn fLine}{\sv 0}}{\sp{\sn lidRegroup}{\sv 1}}{\sp{\sn posrelh}{\sv 0}}{\sp{\sn posrelv}{\sv 0}}{\sp{\sn fLayoutInCell}{\sv 1}}{\sp{\sn fLayoutInCell}{\sv 1}}{\shptxt \ltrpar \pard\plain \ltrpar
+\ql \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs16\alang1025 \ltrch \f1\fs16\cf1\lang1033\langfe1033\cgrid\langnp1033\langfenp1033 {\rtlch \ab\af1\afs22 \ltrch
+\cs16\b\scaps\fs22\expnd3\expndtw18\lang1024\langfe1024\noproof\insrsid7564464 Specifications
+\par }\pard\plain \ltrpar\s24\ql \li0\ri0\sb40\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs17\alang1025 \ltrch \f1\fs17\cf1\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+Part No. TCI-TN65GP-DDRHDLL
+\par }\pard\plain \ltrpar\s15\ql \li0\ri0\widctlpar\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 \rtlch \af1\afs20\alang1025 \ltrch \f1\fs20\cf1\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+\par }\pard\plain \ltrpar\s19\ql \fi-3780\li3780\ri0\sl-210\slmult0\widctlpar\tx180\tx3780\tx4050\tx9180\aspalpha\aspnum\faauto\adjustright\rin0\lin3780\itap0 \rtlch \af1\afs16\alang1025 \ltrch
+\f1\fs16\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464 - Reference input frequency range\tab 220MHz - 1.1GHz
+\par - Slave delay adjustment range\tab 0% - 50% of reference cycle
+\par - Slave delay adjustment resolution\tab 0.83% of reference cycle
+\par - Specified master adjustment setting (MADJ)\tab 120
+\par - Allowed master adjustment range (MADJ)\tab 76 - 256
+\par - Specified slave adjustment range (ADJ)\tab 0 - 60
+\par - Slave delay equation\tab ADJ[7:0]/MADJ[7:0]*Tref
+\par - Number of slaves in cluster\tab 2
+\par - Pulse-width distortion (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Slave delay DNL (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Slave delay INL (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Slave delay jitter (P-P) (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Total slave timing uncertainty (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par
+\par - Power dissipation (nom)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Reset pulse width (min)\tab 1\'b5s
+\par - Lock time (min allowed)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Area (master + 2 slaves, isolation) (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par
+\par - Added core supply package pins\tab 1 VDD and 1 VSS
+\par - Low freq. supply noise est. (P-P) (max)\tab 10% VDD
+\par - Low freq. sub. noise est. (P-P) (max)\tab 10% VDD
+\par - Reference input jitter (period, P-P) (max)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Reference input duty-cycle range\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - High/low slave input pulse width (min)\tab }{\rtlch \af1 \ltrch \i\cf17\insrsid3022649\charrsid3022649 NDA Required}{\rtlch \af1 \ltrch \insrsid3022649
+\par - Slave inputs need not be periodic
+\par - Reference input 10%-90% edge time (max)\tab 150ps
+\par - Slave input 10%-90% edge time (max)\tab 150ps
+\par - Slave output loading (max)\tab 200fF
+\par
+\par - Process technology\tab TSMC CLN65GP 65nm
+\par - Supply voltage (nom, tol)\tab 1.0V, +/-10%
+\par - Junction temperature (nom, min, max)\tab 70C, -40C, 125C
+\par }\pard\plain \ltrpar\s17\ql \fi-72\li72\ri0\sb240\widctlpar\tx72\aspalpha\aspnum\faauto\adjustright\rin0\lin72\itap0 \rtlch \af1\afs13\alang1025 \ltrch \f1\fs13\lang1024\langfe1024\cgrid\noproof\langnp1033\langfenp1033 {\rtlch \af1 \ltrch \insrsid7564464
+*\tab Jitter numbers are worst-case estimates with 10% VDD supply and \line substrate noise\emdash actual results will be better.
+\par }}}}
+{\shp{\*\shpinst\shpleft0\shptop0\shpright11784\shpbottom15364\shpfhdr0\shpbxmargin\shpbxignore\shpbymargin\shpbyignore\shpwr3\shpwrk0\shpfblwtxt0\shpz0\shplid1032{\sp{\sn shapeType}{\sv 75}}{\sp{\sn fFlipH}{\sv 0}}{\sp{\sn fFlipV}{\sv 0}}
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