[Libva] [PATCH] Enable the Bay Trail platform.

[Zhao Halley]

This patch adds PCI IDs for Bay Trail (sometimes called Valley View).
As far as the video driver is concerned, it's very similar to
Ivybridge GT1 except VP8 decoding support.
VP8 decoding support will be added later.
---
 src/i965_render.c  |    2 +-
 src/intel_driver.h |   18 +++++++++++++++++-
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/src/i965_render.c b/src/i965_render.c
index 21ec844..26a7baf 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
@@ -3127,7 +3127,7 @@ i965_render_init(VADriverContextP ctx)
         render_state->max_wm_threads = 204;
     } else if (IS_HSW_GT3(i965->intel.device_id)) {
         render_state->max_wm_threads = 408;
-    } else if (IS_IVB_GT1(i965->intel.device_id)) {
+    } else if (IS_IVB_GT1(i965->intel.device_id) || IS_BAYTRAIL(i965->intel.device_id)) {
         render_state->max_wm_threads = 48;
     } else if (IS_IVB_GT2(i965->intel.device_id)) {
         render_state->max_wm_threads = 172;
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 6f92ce1..19cbc1d 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -238,6 +238,12 @@ struct intel_region
 #define PCI_CHIP_HASWELL_CRW_E_GT2              0x0D1E
 #define PCI_CHIP_HASWELL_CRW_E_GT3              0x0D2E
 
+#define PCI_CHIP_BAYTRAIL_M_1           0x0F31
+#define PCI_CHIP_BAYTRAIL_M_2           0x0F32
+#define PCI_CHIP_BAYTRAIL_M_3           0x0F33
+#define PCI_CHIP_BAYTRAIL_M_4           0x0157
+#define PCI_CHIP_BAYTRAIL_D             0x0155
+
 #define IS_G45(devid)           (devid == PCI_CHIP_IGD_E_G ||   \
                                  devid == PCI_CHIP_Q45_G ||     \
                                  devid == PCI_CHIP_G45_G ||     \
@@ -264,6 +270,15 @@ struct intel_region
 #define IS_GEN6(devid)          (IS_SNB_GT1(devid) ||   \
                                  IS_SNB_GT2(devid))
 
+#define IS_BAYTRAIL_M1(devid)    (devid == PCI_CHIP_BAYTRAIL_M_1)
+#define IS_BAYTRAIL_M2(devid)    (devid == PCI_CHIP_BAYTRAIL_M_2)
+#define IS_BAYTRAIL_M3(devid)    (devid == PCI_CHIP_BAYTRAIL_M_3)
+#define IS_BAYTRAIL_D(devid)     (devid == PCI_CHIP_BAYTRAIL_D)
+#define IS_BAYTRAIL(devid)       (IS_BAYTRAIL_M1(devid) || \
+                                  IS_BAYTRAIL_M2(devid) || \
+                                  IS_BAYTRAIL_M3(devid) || \
+                                  IS_BAYTRAIL_D(devid) )
+
 #define IS_IVB_GT1(devid)       (devid == PCI_CHIP_IVYBRIDGE_GT1 ||     \
                                  devid == PCI_CHIP_IVYBRIDGE_M_GT1 ||   \
                                  devid == PCI_CHIP_IVYBRIDGE_S_GT1)
@@ -273,7 +288,8 @@ struct intel_region
                                  devid == PCI_CHIP_IVYBRIDGE_S_GT2)
 
 #define IS_IVYBRIDGE(devid)     (IS_IVB_GT1(devid) ||   \
-                                 IS_IVB_GT2(devid))
+                                 IS_IVB_GT2(devid) ||   \
+                                 IS_BAYTRAIL(devid) )
 
 #define IS_HSW_GT1(devid)   	(devid == PCI_CHIP_HASWELL_GT1		|| \
                                  devid == PCI_CHIP_HASWELL_M_GT1	|| \
-- 
1.7.9.5