[Libva] [PATCH Intel-driver 1/9] Move all of PCIIDs and codec info into separated files
Xiang, Haihao
haihao.xiang at intel.com
Fri Apr 18 09:21:17 PDT 2014
From: "Xiang, Haihao" <haihao.xiang at intel.com>
The redundant code will be removed soon.
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
---
src/Makefile.am | 2 +
src/i965_device_info.c | 197 +++++++++++++++++++++++++++++++++++++++++++++++++
src/i965_drv_video.c | 172 ++----------------------------------------
src/i965_drv_video.h | 2 +-
src/i965_pciids.h | 131 ++++++++++++++++++++++++++++++++
5 files changed, 336 insertions(+), 168 deletions(-)
create mode 100644 src/i965_device_info.c
create mode 100644 src/i965_pciids.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 7cfb8d4..2d92f4d 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -67,6 +67,7 @@ source_c = \
i965_avc_hw_scoreboard.c\
i965_avc_ildb.c \
i965_decoder_utils.c \
+ i965_device_info.c \
i965_drv_video.c \
i965_encoder.c \
i965_encoder_utils.c \
@@ -109,6 +110,7 @@ source_h = \
i965_media_mpeg2.h \
i965_mutext.h \
i965_gpe_utils.h \
+ i965_pciids.h \
i965_post_processing.h \
i965_render.h \
i965_structs.h \
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
new file mode 100644
index 0000000..810e42b
--- /dev/null
+++ b/src/i965_device_info.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "i965_drv_video.h"
+
+extern struct hw_context *i965_proc_context_init(VADriverContextP, struct object_config *);
+extern struct hw_context *g4x_dec_hw_context_init(VADriverContextP, struct object_config *);
+static const struct hw_codec_info g4x_hw_codec_info = {
+ .dec_hw_context_init = g4x_dec_hw_context_init,
+ .enc_hw_context_init = NULL,
+ .proc_hw_context_init = NULL,
+ .max_width = 2048,
+ .max_height = 2048,
+
+ .has_mpeg2_decoding = 1,
+
+ .num_filters = 0,
+};
+
+extern struct hw_context *ironlake_dec_hw_context_init(VADriverContextP, struct object_config *);
+static const struct hw_codec_info ilk_hw_codec_info = {
+ .dec_hw_context_init = ironlake_dec_hw_context_init,
+ .enc_hw_context_init = NULL,
+ .proc_hw_context_init = i965_proc_context_init,
+ .max_width = 2048,
+ .max_height = 2048,
+
+ .has_mpeg2_decoding = 1,
+ .has_h264_decoding = 1,
+ .has_vpp = 1,
+ .has_accelerated_putimage = 1,
+
+ .num_filters = 0,
+};
+
+extern struct hw_context *gen6_dec_hw_context_init(VADriverContextP, struct object_config *);
+extern struct hw_context *gen6_enc_hw_context_init(VADriverContextP, struct object_config *);
+static const struct hw_codec_info snb_hw_codec_info = {
+ .dec_hw_context_init = gen6_dec_hw_context_init,
+ .enc_hw_context_init = gen6_enc_hw_context_init,
+ .proc_hw_context_init = i965_proc_context_init,
+ .max_width = 2048,
+ .max_height = 2048,
+
+ .has_mpeg2_decoding = 1,
+ .has_mpeg2_encoding = 1,
+ .has_h264_decoding = 1,
+ .has_h264_encoding = 1,
+ .has_vc1_decoding = 1,
+ .has_vpp = 1,
+ .has_accelerated_getimage = 1,
+ .has_accelerated_putimage = 1,
+ .has_tiled_surface = 1,
+
+ .num_filters = 2,
+ .filters = {
+ { VAProcFilterNoiseReduction, I965_RING_NULL },
+ { VAProcFilterDeinterlacing, I965_RING_NULL },
+ },
+};
+
+extern struct hw_context *gen7_dec_hw_context_init(VADriverContextP, struct object_config *);
+extern struct hw_context *gen7_enc_hw_context_init(VADriverContextP, struct object_config *);
+static const struct hw_codec_info ivb_hw_codec_info = {
+ .dec_hw_context_init = gen7_dec_hw_context_init,
+ .enc_hw_context_init = gen7_enc_hw_context_init,
+ .proc_hw_context_init = i965_proc_context_init,
+ .max_width = 4096,
+ .max_height = 4096,
+
+ .has_mpeg2_decoding = 1,
+ .has_mpeg2_encoding = 1,
+ .has_h264_decoding = 1,
+ .has_h264_encoding = 1,
+ .has_vc1_decoding = 1,
+ .has_jpeg_decoding = 1,
+ .has_vpp = 1,
+ .has_accelerated_getimage = 1,
+ .has_accelerated_putimage = 1,
+ .has_tiled_surface = 1,
+ .has_di_motion_adptive = 1,
+ .has_blending = 1,
+
+ .num_filters = 2,
+ .filters = {
+ { VAProcFilterNoiseReduction, I965_RING_NULL },
+ { VAProcFilterDeinterlacing, I965_RING_NULL },
+ },
+};
+
+extern struct hw_context *gen75_dec_hw_context_init(VADriverContextP, struct object_config *);
+extern struct hw_context *gen75_enc_hw_context_init(VADriverContextP, struct object_config *);
+extern struct hw_context *gen75_proc_context_init(VADriverContextP, struct object_config *);
+static const struct hw_codec_info hsw_hw_codec_info = {
+ .dec_hw_context_init = gen75_dec_hw_context_init,
+ .enc_hw_context_init = gen75_enc_hw_context_init,
+ .proc_hw_context_init = gen75_proc_context_init,
+ .max_width = 4096,
+ .max_height = 4096,
+
+ .has_mpeg2_decoding = 1,
+ .has_mpeg2_encoding = 1,
+ .has_h264_decoding = 1,
+ .has_h264_encoding = 1,
+ .has_vc1_decoding = 1,
+ .has_jpeg_decoding = 1,
+ .has_vpp = 1,
+ .has_accelerated_getimage = 1,
+ .has_accelerated_putimage = 1,
+ .has_tiled_surface = 1,
+ .has_di_motion_adptive = 1,
+ .has_di_motion_compensated = 1,
+ .has_blending = 1,
+ .has_h264_mvc_decoding = 1,
+ .has_h264_mvc_encoding = 1,
+
+ .num_filters = 5,
+ .filters = {
+ { VAProcFilterNoiseReduction, I965_RING_VEBOX },
+ { VAProcFilterDeinterlacing, I965_RING_VEBOX },
+ { VAProcFilterSharpening, I965_RING_NULL },
+ { VAProcFilterColorBalance, I965_RING_VEBOX},
+ { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
+ },
+};
+
+extern struct hw_context *gen8_dec_hw_context_init(VADriverContextP, struct object_config *);
+extern struct hw_context *gen8_enc_hw_context_init(VADriverContextP, struct object_config *);
+static const struct hw_codec_info bdw_hw_codec_info = {
+ .dec_hw_context_init = gen8_dec_hw_context_init,
+ .enc_hw_context_init = gen8_enc_hw_context_init,
+ .proc_hw_context_init = gen75_proc_context_init,
+ .max_width = 4096,
+ .max_height = 4096,
+
+ .has_mpeg2_decoding = 1,
+ .has_mpeg2_encoding = 1,
+ .has_h264_decoding = 1,
+ .has_h264_encoding = 1,
+ .has_vc1_decoding = 1,
+ .has_jpeg_decoding = 1,
+ .has_vpp = 1,
+ .has_accelerated_getimage = 1,
+ .has_accelerated_putimage = 1,
+ .has_tiled_surface = 1,
+ .has_di_motion_adptive = 1,
+ .has_di_motion_compensated = 1,
+ .has_vp8_decoding = 1,
+ .has_blending = 1,
+ .has_h264_mvc_decoding = 1,
+ .has_h264_mvc_encoding = 1,
+
+ .num_filters = 5,
+ .filters = {
+ { VAProcFilterNoiseReduction, I965_RING_VEBOX },
+ { VAProcFilterDeinterlacing, I965_RING_VEBOX },
+ { VAProcFilterSharpening, I965_RING_NULL }, /* need to rebuild the shader for BDW */
+ { VAProcFilterColorBalance, I965_RING_VEBOX},
+ { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
+ },
+};
+
+const struct hw_codec_info *
+i965_get_codec_info(int devid)
+{
+ switch (devid) {
+#undef CHIPSET
+#define CHIPSET(id, family, dev, str) case id: return &family##_hw_codec_info;
+#include "i965_pciids.h"
+ default:
+ return NULL;
+ }
+}
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 6032a36..27d6d38 100755
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -221,160 +221,6 @@ get_subpic_format(const VAImageFormat *va_format)
return NULL;
}
-extern struct hw_context *i965_proc_context_init(VADriverContextP, struct object_config *);
-extern struct hw_context *g4x_dec_hw_context_init(VADriverContextP, struct object_config *);
-static struct hw_codec_info g4x_hw_codec_info = {
- .dec_hw_context_init = g4x_dec_hw_context_init,
- .enc_hw_context_init = NULL,
- .proc_hw_context_init = NULL,
- .max_width = 2048,
- .max_height = 2048,
-
- .has_mpeg2_decoding = 1,
-
- .num_filters = 0,
-};
-
-extern struct hw_context *ironlake_dec_hw_context_init(VADriverContextP, struct object_config *);
-static struct hw_codec_info ironlake_hw_codec_info = {
- .dec_hw_context_init = ironlake_dec_hw_context_init,
- .enc_hw_context_init = NULL,
- .proc_hw_context_init = i965_proc_context_init,
- .max_width = 2048,
- .max_height = 2048,
-
- .has_mpeg2_decoding = 1,
- .has_h264_decoding = 1,
- .has_vpp = 1,
- .has_accelerated_putimage = 1,
-
- .num_filters = 0,
-};
-
-extern struct hw_context *gen6_dec_hw_context_init(VADriverContextP, struct object_config *);
-extern struct hw_context *gen6_enc_hw_context_init(VADriverContextP, struct object_config *);
-static struct hw_codec_info gen6_hw_codec_info = {
- .dec_hw_context_init = gen6_dec_hw_context_init,
- .enc_hw_context_init = gen6_enc_hw_context_init,
- .proc_hw_context_init = i965_proc_context_init,
- .max_width = 2048,
- .max_height = 2048,
-
- .has_mpeg2_decoding = 1,
- .has_mpeg2_encoding = 1,
- .has_h264_decoding = 1,
- .has_h264_encoding = 1,
- .has_vc1_decoding = 1,
- .has_vpp = 1,
- .has_accelerated_getimage = 1,
- .has_accelerated_putimage = 1,
- .has_tiled_surface = 1,
-
- .num_filters = 2,
- .filters = {
- { VAProcFilterNoiseReduction, I965_RING_NULL },
- { VAProcFilterDeinterlacing, I965_RING_NULL },
- },
-};
-
-extern struct hw_context *gen7_dec_hw_context_init(VADriverContextP, struct object_config *);
-extern struct hw_context *gen7_enc_hw_context_init(VADriverContextP, struct object_config *);
-static struct hw_codec_info gen7_hw_codec_info = {
- .dec_hw_context_init = gen7_dec_hw_context_init,
- .enc_hw_context_init = gen7_enc_hw_context_init,
- .proc_hw_context_init = i965_proc_context_init,
- .max_width = 4096,
- .max_height = 4096,
-
- .has_mpeg2_decoding = 1,
- .has_mpeg2_encoding = 1,
- .has_h264_decoding = 1,
- .has_h264_encoding = 1,
- .has_vc1_decoding = 1,
- .has_jpeg_decoding = 1,
- .has_vpp = 1,
- .has_accelerated_getimage = 1,
- .has_accelerated_putimage = 1,
- .has_tiled_surface = 1,
- .has_di_motion_adptive = 1,
- .has_blending = 1,
-
- .num_filters = 2,
- .filters = {
- { VAProcFilterNoiseReduction, I965_RING_NULL },
- { VAProcFilterDeinterlacing, I965_RING_NULL },
- },
-};
-
-extern struct hw_context *gen75_proc_context_init(VADriverContextP, struct object_config *);
-static struct hw_codec_info gen75_hw_codec_info = {
- .dec_hw_context_init = gen75_dec_hw_context_init,
- .enc_hw_context_init = gen75_enc_hw_context_init,
- .proc_hw_context_init = gen75_proc_context_init,
- .max_width = 4096,
- .max_height = 4096,
-
- .has_mpeg2_decoding = 1,
- .has_mpeg2_encoding = 1,
- .has_h264_decoding = 1,
- .has_h264_encoding = 1,
- .has_vc1_decoding = 1,
- .has_jpeg_decoding = 1,
- .has_vpp = 1,
- .has_accelerated_getimage = 1,
- .has_accelerated_putimage = 1,
- .has_tiled_surface = 1,
- .has_di_motion_adptive = 1,
- .has_di_motion_compensated = 1,
- .has_blending = 1,
- .has_h264_mvc_decoding = 1,
- .has_h264_mvc_encoding = 1,
-
- .num_filters = 5,
- .filters = {
- { VAProcFilterNoiseReduction, I965_RING_VEBOX },
- { VAProcFilterDeinterlacing, I965_RING_VEBOX },
- { VAProcFilterSharpening, I965_RING_NULL },
- { VAProcFilterColorBalance, I965_RING_VEBOX},
- { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
- },
-};
-
-/* TODO: Add the separate call back function for Gen8 */
-static struct hw_codec_info gen8_hw_codec_info = {
- .dec_hw_context_init = gen8_dec_hw_context_init,
- .enc_hw_context_init = gen8_enc_hw_context_init,
- .proc_hw_context_init = gen75_proc_context_init,
- .max_width = 4096,
- .max_height = 4096,
-
- .has_mpeg2_decoding = 1,
- .has_mpeg2_encoding = 1,
- .has_h264_decoding = 1,
- .has_h264_encoding = 1,
- .has_vc1_decoding = 1,
- .has_jpeg_decoding = 1,
- .has_vpp = 1,
- .has_accelerated_getimage = 1,
- .has_accelerated_putimage = 1,
- .has_tiled_surface = 1,
- .has_di_motion_adptive = 1,
- .has_di_motion_compensated = 1,
- .has_vp8_decoding = 1,
- .has_blending = 1,
- .has_h264_mvc_decoding = 1,
- .has_h264_mvc_encoding = 1,
-
- .num_filters = 5,
- .filters = {
- { VAProcFilterNoiseReduction, I965_RING_VEBOX },
- { VAProcFilterDeinterlacing, I965_RING_VEBOX },
- { VAProcFilterSharpening, I965_RING_NULL }, /* need to rebuild the shader for BDW */
- { VAProcFilterColorBalance, I965_RING_VEBOX},
- { VAProcFilterSkinToneEnhancement, I965_RING_VEBOX},
- },
-};
-
#define I965_PACKED_HEADER_BASE 0
#define I965_PACKED_MISC_HEADER_BASE 3
@@ -5183,24 +5029,16 @@ VAStatus i965_QueryVideoProcPipelineCaps(
return VA_STATUS_SUCCESS;
}
+extern const struct hw_codec_info *i965_get_codec_info(int devid);
+
static bool
i965_driver_data_init(VADriverContextP ctx)
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
- if (IS_GEN8(i965->intel.device_id))
- i965->codec_info = &gen8_hw_codec_info;
- else if (IS_HASWELL(i965->intel.device_id))
- i965->codec_info = &gen75_hw_codec_info;
- else if (IS_G4X(i965->intel.device_id))
- i965->codec_info = &g4x_hw_codec_info;
- else if (IS_IRONLAKE(i965->intel.device_id))
- i965->codec_info = &ironlake_hw_codec_info;
- else if (IS_GEN6(i965->intel.device_id))
- i965->codec_info = &gen6_hw_codec_info;
- else if (IS_GEN7(i965->intel.device_id))
- i965->codec_info = &gen7_hw_codec_info;
- else
+ i965->codec_info = i965_get_codec_info(i965->intel.device_id);
+
+ if (!i965->codec_info)
return false;
if (object_heap_init(&i965->config_heap,
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index 2c217a7..b976d33 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -325,7 +325,7 @@ struct i965_driver_data
struct object_heap buffer_heap;
struct object_heap image_heap;
struct object_heap subpic_heap;
- struct hw_codec_info *codec_info;
+ const struct hw_codec_info *codec_info;
_I965Mutex render_mutex;
_I965Mutex pp_mutex;
diff --git a/src/i965_pciids.h b/src/i965_pciids.h
new file mode 100644
index 0000000..64973e4
--- /dev/null
+++ b/src/i965_pciids.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Copied and modified from (mesa) include/pci_ids/i965_pci_ids.h
+ */
+
+CHIPSET(0x2A42, g4x, g4x, "Intel(R) GM45 Express Chipset")
+CHIPSET(0x2E02, g4x, g4x, "Intel(R) Integrated Graphics Device")
+CHIPSET(0x2E12, g4x, g4x, "Intel(R) Q45/Q43")
+CHIPSET(0x2E22, g4x, g4x, "Intel(R) G45/G43")
+CHIPSET(0x2E32, g4x, g4x, "Intel(R) G41")
+CHIPSET(0x2E42, g4x, g4x, "Intel(R) B43")
+CHIPSET(0x2E92, g4x, g4x, "Intel(R) B43")
+CHIPSET(0x0042, ilk, ilk, "Intel(R) Ironlake Desktop")
+CHIPSET(0x0046, ilk, ilk, "Intel(R) Ironlake Mobile")
+CHIPSET(0x0102, snb, snb_gt1, "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0112, snb, snb_gt2, "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0122, snb, snb_gt2, "Intel(R) Sandybridge Desktop")
+CHIPSET(0x0106, snb, snb_gt1, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x0116, snb, snb_gt2, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x0126, snb, snb_gt2, "Intel(R) Sandybridge Mobile")
+CHIPSET(0x010A, snb, snb_gt1, "Intel(R) Sandybridge Server")
+CHIPSET(0x0152, ivb, ivb_gt1, "Intel(R) Ivybridge Desktop")
+CHIPSET(0x0162, ivb, ivb_gt2, "Intel(R) Ivybridge Desktop")
+CHIPSET(0x0156, ivb, ivb_gt1, "Intel(R) Ivybridge Mobile")
+CHIPSET(0x0166, ivb, ivb_gt2, "Intel(R) Ivybridge Mobile")
+CHIPSET(0x015A, ivb, ivb_gt1, "Intel(R) Ivybridge Server")
+CHIPSET(0x016A, ivb, ivb_gt2, "Intel(R) Ivybridge Server")
+CHIPSET(0x0F31, ivb, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F32, ivb, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0F33, ivb, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0157, ivb, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0155, ivb, byt, "Intel(R) Bay Trail")
+CHIPSET(0x0402, hsw, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0412, hsw, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0422, hsw, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0406, hsw, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0416, hsw, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0426, hsw, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x040A, hsw, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x041A, hsw, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x042A, hsw, hsw_gt3, "Intel(R) Haswell Server")
+CHIPSET(0x040B, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x041B, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x042B, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x040E, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x041E, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x042E, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0C02, hsw, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0C12, hsw, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0C22, hsw, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0C06, hsw, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0C16, hsw, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0C26, hsw, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x0C0A, hsw, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x0C1A, hsw, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x0C2A, hsw, hsw_gt3, "Intel(R) Haswell Server")
+CHIPSET(0x0C0B, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0C1B, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0C2B, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0C0E, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0C1E, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0C2E, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0A02, hsw, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0A12, hsw, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0A22, hsw, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0A06, hsw, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0A16, hsw, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0A26, hsw, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x0A0A, hsw, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x0A1A, hsw, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x0A2A, hsw, hsw_gt3, "Intel(R) Haswell Server")
+CHIPSET(0x0A0B, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0A1B, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0A2B, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0A0E, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0A1E, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0A2E, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0D02, hsw, hsw_gt1, "Intel(R) Haswell Desktop")
+CHIPSET(0x0D12, hsw, hsw_gt2, "Intel(R) Haswell Desktop")
+CHIPSET(0x0D22, hsw, hsw_gt3, "Intel(R) Haswell Desktop")
+CHIPSET(0x0D06, hsw, hsw_gt1, "Intel(R) Haswell Mobile")
+CHIPSET(0x0D16, hsw, hsw_gt2, "Intel(R) Haswell Mobile")
+CHIPSET(0x0D26, hsw, hsw_gt3, "Intel(R) Haswell Mobile")
+CHIPSET(0x0D0A, hsw, hsw_gt1, "Intel(R) Haswell Server")
+CHIPSET(0x0D1A, hsw, hsw_gt2, "Intel(R) Haswell Server")
+CHIPSET(0x0D2A, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0D0B, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0D1B, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0D2B, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x0D0E, hsw, hsw_gt1, "Intel(R) Haswell")
+CHIPSET(0x0D1E, hsw, hsw_gt2, "Intel(R) Haswell")
+CHIPSET(0x0D2E, hsw, hsw_gt3, "Intel(R) Haswell")
+CHIPSET(0x1602, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x1606, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x160A, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x160B, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x160D, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x160E, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x1612, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x1616, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x161A, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x161B, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x161D, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x161E, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x1622, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x1626, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x162A, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x162B, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x162D, bdw, bdw, "Intel(R) Broadwell")
+CHIPSET(0x162E, bdw, bdw, "Intel(R) Broadwell")
--
1.8.3.2
More information about the Libva
mailing list