[Libva] [Libva-intel-driver PATCH 3/6] Decode: Dump the registers related with decoding when GPU hang is triggered on Ivy/Haswell

[Zhao, Yakui]

From: Zhao Yakui <yakui.zhao at intel.com>

Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
 src/i965_drv_video.c |   60 ++++++++++++++++++++++++++++++++++++++++++++++++++
 src/i965_drv_video.h |    1 +
 src/intel_driver.h   |   20 +++++++++++++++++
 3 files changed, 81 insertions(+)

diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index be9edff..ead82a8 100755
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1697,6 +1697,10 @@ i965_destroy_context(struct object_heap *heap, struct object_base *obj)
         assert(obj_context->codec_state.decode.num_slice_params <= obj_context->codec_state.decode.max_slice_params);
         assert(obj_context->codec_state.decode.num_slice_datas <= obj_context->codec_state.decode.max_slice_datas);
 
+        if (obj_context->codec_state.decode.vdbox_reg) {
+            dri_bo_unreference(obj_context->codec_state.decode.vdbox_reg);
+            obj_context->codec_state.decode.vdbox_reg = NULL;
+        }
         i965_release_buffer_store(&obj_context->codec_state.decode.pic_param);
         i965_release_buffer_store(&obj_context->codec_state.decode.iq_matrix);
         i965_release_buffer_store(&obj_context->codec_state.decode.bit_plane);
@@ -1859,6 +1863,10 @@ i965_CreateContext(VADriverContextP ctx,
 
             assert(i965->codec_info->dec_hw_context_init);
             obj_context->hw_context = i965->codec_info->dec_hw_context_init(ctx, obj_config);
+            obj_context->codec_state.decode.vdbox_reg = dri_bo_alloc(i965->intel.bufmgr,
+                                       "dump reg",
+                                       0x1000,
+                                       0x1000);
         }
     }
 
@@ -2749,6 +2757,55 @@ i965_RenderPicture(VADriverContextP ctx,
     return vaStatus;
 }
 
+static const mfd_reg dump_regs[] =
+{
+	{MFD_ERROR_STATUS, "Error_status" },
+	{MFD_PICTURE_PARM, "Picture_levle_param" },
+	{MFD_PIPELINE_STATUS, "Pipeline_status" },
+	{MFD_ERROR_INJECTION, "HW Error injection"},
+	{MFD_FRAME_PERF_COUNT, "Frame Performance count" },
+	{MFD_SLICE_PERF_COUNT, "Slice Performance count" },
+	{MFD_FRAME_MACROBLOCK_COUNT, "Number of MB per frame" },
+	{MFD_FRAME_BSE_COUNT, "Number of Bin per frame" },
+};
+
+void dump_decoding_register(VADriverContextP ctx, dri_bo *bo)
+{
+    struct i965_driver_data *i965 = i965_driver_data(ctx);
+    struct intel_batchbuffer *batch = i965->batch;
+
+    int i, dump_count;
+    unsigned int *ptr;
+
+    if (IS_HASWELL(i965->intel.device_info) || IS_GEN7(i965->intel.device_info)) {
+
+        dump_count = sizeof(dump_regs) / sizeof(mfd_reg);
+
+	intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
+
+        for (i = 0; i < dump_count; i++) {
+            BEGIN_BCS_BATCH(batch, 3);
+            OUT_BCS_BATCH(batch, MI_STORE_REG_IMM | (0 << 22) | 1);
+            OUT_BCS_BATCH(batch, GEN7_MFD_BASE_OFFSET + dump_regs[i].reg_offset);
+            OUT_BCS_RELOC(batch, bo, I915_GEM_DOMAIN_INSTRUCTION, 0, i * 4);
+            ADVANCE_BCS_BATCH(batch);
+	}
+	intel_batchbuffer_end_atomic(batch);
+	intel_batchbuffer_flush(batch);
+
+
+    	dri_bo_map(bo, 0);
+    	ptr = bo->virtual;
+	for (i = 0; i < dump_count; i++) {
+	    fprintf(stderr, "the value of Reg %8x (%s) is %x\n",
+		    dump_regs[i].reg_offset + GEN7_MFD_BASE_OFFSET,
+		    dump_regs[i].name, *(ptr + i));
+	}
+	dri_bo_unmap(bo);
+    }
+
+}
+
 VAStatus 
 i965_EndPicture(VADriverContextP ctx, VAContextID context)
 {
@@ -2828,9 +2885,12 @@ i965_EndPicture(VADriverContextP ctx, VAContextID context)
         f_end_time = f_end_time / 1000000000 + end_time.tv_sec;
 
         if ((f_end_time - f_begin_time) >= 2.0) {
+
             fprintf(stderr, "GPU hang is triggered on frame %d \t\n",
                     obj_context->codec_state.decode.frame_no);
 
+            dump_decoding_register(ctx, obj_context->codec_state.decode.vdbox_reg);
+
         }
 
         obj_context->codec_state.decode.frame_no++;
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index d12f696..be1eeda 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -131,6 +131,7 @@ struct decode_state
 
     int frame_no;
     struct timespec frame_begin_time;
+    dri_bo *vdbox_reg;
 };
 
 #define SLICE_PACKED_DATA_INDEX_TYPE    0x80000000
diff --git a/src/intel_driver.h b/src/intel_driver.h
index 5d7d043..9df9e8d 100644
--- a/src/intel_driver.h
+++ b/src/intel_driver.h
@@ -33,6 +33,8 @@
 #define MI_FLUSH_DW                             (CMD_MI | (0x26 << 23) | 0x2)
 #define   MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE   (0x1 << 7)
 
+#define MI_STORE_REG_IMM		        (CMD_MI | (0x24 << 23))
+
 #define XY_COLOR_BLT_CMD                        (CMD_2D | (0x50 << 22) | 0x04)
 #define XY_COLOR_BLT_WRITE_ALPHA                (1 << 21)
 #define XY_COLOR_BLT_WRITE_RGB                  (1 << 20)
@@ -196,4 +198,22 @@ struct intel_region
 #define I915_EXEC_VEBOX         4
 #endif
 
+#define GEN7_MFD_BASE_OFFSET		0x12400
+
+#define MFD_ERROR_STATUS		0x0
+#define MFD_PICTURE_PARM		0x20
+#define MFD_PIPELINE_STATUS		0x38
+#define MFD_ERROR_INJECTION		0x54
+#define MFD_FRAME_PERF_COUNT		0x60
+#define MFD_SLICE_PERF_COUNT		0x64
+#define MFD_FRAME_MACROBLOCK_COUNT	0x68
+#define MFD_FRAME_BSE_COUNT		0x6c
+#define MFD_MC_READ_COUNT		0x84
+#define MFD_MC_MISS_COUNT		0x88
+
+typedef struct _mfd_reg_ {
+	uint32_t reg_offset;
+	char *name;
+} mfd_reg;
+
 #endif /* _INTEL_DRIVER_H_ */
-- 
1.7.10.1