[Libva] [PATCH][libva-intel-driver] VPP: MADI on SNB
Xiang, Haihao
haihao.xiang at intel.com
Mon May 19 01:47:12 PDT 2014
From: "Xiang, Haihao" <haihao.xiang at intel.com>
Set the right surface states for reference, STMM and output surface,
fix the shader as well
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
---
src/i965_device_info.c | 1 +
src/i965_post_processing.c | 171 ++++++++++++++++-----
.../Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm | 43 +++---
.../post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 | 37 +++--
.../post_processing/gen5_6/nv12_dndi_nv12.g6b | 37 +++--
5 files changed, 203 insertions(+), 86 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index 505cd5a..50aa664 100644
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -94,6 +94,7 @@ static const struct hw_codec_info snb_hw_codec_info = {
.has_accelerated_getimage = 1,
.has_accelerated_putimage = 1,
.has_tiled_surface = 1,
+ .has_di_motion_adptive = 1,
.num_filters = 2,
.filters = {
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
index 9bfcf49..8999266 100755
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -40,6 +40,11 @@
#include "i965_render.h"
#include "intel_media.h"
+extern VAStatus
+vpp_surface_convert(VADriverContextP ctx,
+ struct object_surface *src_obj_surf,
+ struct object_surface *dst_obj_surf);
+
#define HAS_BLENDING(ctx) ((ctx)->codec_info->has_blending)
#define HAS_VPP(ctx) ((ctx)->codec_info->has_vpp)
@@ -3064,13 +3069,14 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
struct pp_dndi_context *pp_dndi_context = (struct pp_dndi_context *)&pp_context->pp_dndi_context;
struct pp_inline_parameter *pp_inline_parameter = pp_context->pp_inline_parameter;
struct pp_static_parameter *pp_static_parameter = pp_context->pp_static_parameter;
- struct object_surface *obj_surface;
+ struct object_surface *previous_in_obj_surface, *current_in_obj_surface, *previous_out_obj_surface, *current_out_obj_surface;
struct i965_sampler_dndi *sampler_dndi;
int index;
int w, h;
int orig_w, orig_h;
int dndi_top_first = 1;
VAProcFilterParameterBufferDeinterlacing *di_filter_param = (VAProcFilterParameterBufferDeinterlacing *)filter_param;
+ int is_first_frame = (pp_dndi_context->frame_order == -1);
if (di_filter_param->flags & VA_DEINTERLACING_BOTTOM_FIELD)
dndi_top_first = 0;
@@ -3078,58 +3084,159 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
dndi_top_first = 1;
/* surface */
- obj_surface = (struct object_surface *)src_surface->base;
- orig_w = obj_surface->orig_width;
- orig_h = obj_surface->orig_height;
- w = obj_surface->width;
- h = obj_surface->height;
+ current_in_obj_surface = (struct object_surface *)src_surface->base;
- if (pp_dndi_context->stmm_bo == NULL) {
- pp_dndi_context->stmm_bo = dri_bo_alloc(i965->intel.bufmgr,
- "STMM surface",
- w * h,
- 4096);
- assert(pp_dndi_context->stmm_bo);
+ if (di_filter_param->algorithm == VAProcDeinterlacingBob) {
+ previous_in_obj_surface = current_in_obj_surface;
+ is_first_frame = 1;
+ } else if (di_filter_param->algorithm == VAProcDeinterlacingMotionAdaptive) {
+ if (pp_dndi_context->frame_order == 0) {
+ VAProcPipelineParameterBuffer *pipeline_param = pp_context->pipeline_param;
+ if (!pipeline_param ||
+ !pipeline_param->num_forward_references ||
+ pipeline_param->forward_references[0] == VA_INVALID_ID) {
+ WARN_ONCE("A forward temporal reference is needed for Motion adaptive deinterlacing !!!\n");
+
+ return VA_STATUS_ERROR_INVALID_PARAMETER;
+ } else {
+ previous_in_obj_surface = SURFACE(pipeline_param->forward_references[0]);
+ assert(previous_in_obj_surface && previous_in_obj_surface->bo);
+
+ is_first_frame = 0;
+ }
+ } else if (pp_dndi_context->frame_order == 1) {
+ vpp_surface_convert(ctx,
+ pp_dndi_context->current_out_obj_surface,
+ (struct object_surface *)dst_surface->base);
+ pp_dndi_context->frame_order = (pp_dndi_context->frame_order + 1) % 2;
+ is_first_frame = 0;
+
+ return VA_STATUS_SUCCESS_1;
+ } else {
+ previous_in_obj_surface = current_in_obj_surface;
+ is_first_frame = 1;
+ }
+ } else {
+ return VA_STATUS_ERROR_UNIMPLEMENTED;
}
+ /* source (temporal reference) YUV surface index 5 */
+ orig_w = previous_in_obj_surface->orig_width;
+ orig_h = previous_in_obj_surface->orig_height;
+ w = previous_in_obj_surface->width;
+ h = previous_in_obj_surface->height;
+ i965_pp_set_surface2_state(ctx, pp_context,
+ previous_in_obj_surface->bo, 0,
+ orig_w, orig_h, w,
+ 0, h,
+ SURFACE_FORMAT_PLANAR_420_8, 1,
+ 5);
+
+ /* source surface */
+ orig_w = current_in_obj_surface->orig_width;
+ orig_h = current_in_obj_surface->orig_height;
+ w = current_in_obj_surface->width;
+ h = current_in_obj_surface->height;
+
/* source UV surface index 2 */
i965_pp_set_surface_state(ctx, pp_context,
- obj_surface->bo, w * h,
+ current_in_obj_surface->bo, w * h,
orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
2, 0);
/* source YUV surface index 4 */
i965_pp_set_surface2_state(ctx, pp_context,
- obj_surface->bo, 0,
+ current_in_obj_surface->bo, 0,
orig_w, orig_h, w,
0, h,
SURFACE_FORMAT_PLANAR_420_8, 1,
4);
- /* source STMM surface index 20 */
+ /* source STMM surface index 6 */
+ if (pp_dndi_context->stmm_bo == NULL) {
+ pp_dndi_context->stmm_bo = dri_bo_alloc(i965->intel.bufmgr,
+ "STMM surface",
+ w * h,
+ 4096);
+ assert(pp_dndi_context->stmm_bo);
+ }
+
i965_pp_set_surface_state(ctx, pp_context,
pp_dndi_context->stmm_bo, 0,
orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
- 20, 1);
+ 6, 0);
- /* destination surface */
- obj_surface = (struct object_surface *)dst_surface->base;
- orig_w = obj_surface->orig_width;
- orig_h = obj_surface->orig_height;
- w = obj_surface->width;
- h = obj_surface->height;
+ /* destination (Previous frame) */
+ previous_out_obj_surface = (struct object_surface *)dst_surface->base;
+ orig_w = previous_out_obj_surface->orig_width;
+ orig_h = previous_out_obj_surface->orig_height;
+ w = previous_out_obj_surface->width;
+ h = previous_out_obj_surface->height;
- /* destination Y surface index 7 */
+ if (is_first_frame) {
+ current_out_obj_surface = previous_out_obj_surface;
+ } else {
+ VAStatus va_status;
+
+ if (pp_dndi_context->current_out_surface == VA_INVALID_SURFACE) {
+ unsigned int tiling = 0, swizzle = 0;
+ dri_bo_get_tiling(previous_out_obj_surface->bo, &tiling, &swizzle);
+
+ va_status = i965_CreateSurfaces(ctx,
+ orig_w,
+ orig_h,
+ VA_RT_FORMAT_YUV420,
+ 1,
+ &pp_dndi_context->current_out_surface);
+ assert(va_status == VA_STATUS_SUCCESS);
+ pp_dndi_context->current_out_obj_surface = SURFACE(pp_dndi_context->current_out_surface);
+ assert(pp_dndi_context->current_out_obj_surface);
+ i965_check_alloc_surface_bo(ctx,
+ pp_dndi_context->current_out_obj_surface,
+ tiling != I915_TILING_NONE,
+ VA_FOURCC_NV12,
+ SUBSAMPLE_YUV420);
+ }
+
+ current_out_obj_surface = pp_dndi_context->current_out_obj_surface;
+ }
+
+ /* destination (Previous frame) Y surface index 7 */
i965_pp_set_surface_state(ctx, pp_context,
- obj_surface->bo, 0,
+ previous_out_obj_surface->bo, 0,
orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
7, 1);
- /* destination UV surface index 8 */
+ /* destination (Previous frame) UV surface index 8 */
i965_pp_set_surface_state(ctx, pp_context,
- obj_surface->bo, w * h,
+ previous_out_obj_surface->bo, w * h,
orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
8, 1);
+
+ /* destination(Current frame) */
+ orig_w = current_out_obj_surface->orig_width;
+ orig_h = current_out_obj_surface->orig_height;
+ w = current_out_obj_surface->width;
+ h = current_out_obj_surface->height;
+
+ /* destination (Current frame) Y surface index xxx */
+ i965_pp_set_surface_state(ctx, pp_context,
+ current_out_obj_surface->bo, 0,
+ orig_w / 4, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
+ 10, 1);
+
+ /* destination (Current frame) UV surface index xxx */
+ i965_pp_set_surface_state(ctx, pp_context,
+ current_out_obj_surface->bo, w * h,
+ orig_w / 4, orig_h / 2, w, I965_SURFACEFORMAT_R8G8_UNORM,
+ 11, 1);
+
+ /* STMM output surface, index 20 */
+ i965_pp_set_surface_state(ctx, pp_context,
+ pp_dndi_context->stmm_bo, 0,
+ orig_w, orig_h, w, I965_SURFACEFORMAT_R8_UNORM,
+ 20, 1);
+
/* sampler dndi */
dri_bo_map(pp_context->sampler_state_table.bo, True);
assert(pp_context->sampler_state_table.bo->virtual);
@@ -3177,7 +3284,7 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
sampler_dndi[index].dw6.di_partial = 0;
sampler_dndi[index].dw6.dndi_top_first = dndi_top_first;
sampler_dndi[index].dw6.dndi_stream_id = 0;
- sampler_dndi[index].dw6.dndi_first_frame = 1;
+ sampler_dndi[index].dw6.dndi_first_frame = is_first_frame;
sampler_dndi[index].dw6.progressive_dn = 0;
sampler_dndi[index].dw6.fmd_tear_threshold = 2;
sampler_dndi[index].dw6.fmd2_vertical_difference_threshold = 100;
@@ -3211,6 +3318,8 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_contex
dst_surface->flags = I965_SURFACE_FLAG_FRAME;
+ pp_dndi_context->frame_order = (pp_dndi_context->frame_order + 1) % 2;
+
return VA_STATUS_SUCCESS;
}
@@ -3448,12 +3557,6 @@ gen7_pp_dndi_set_block_parameter(struct i965_post_processing_context *pp_context
return 0;
}
-
-extern VAStatus
-vpp_surface_convert(VADriverContextP ctx,
- struct object_surface *src_obj_surf,
- struct object_surface *dst_obj_surf);
-
static VAStatus
gen7_pp_nv12_dndi_initialize(VADriverContextP ctx, struct i965_post_processing_context *pp_context,
const struct i965_surface *src_surface,
@@ -5447,8 +5550,6 @@ static const int proc_frame_to_pp_frame[3] = {
I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST
};
-#define VA_STATUS_SUCCESS_1 0xFFFFFFFE
-
VAStatus
i965_proc_picture(VADriverContextP ctx,
VAProfile profile,
diff --git a/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm b/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
index 280d37a..23bd306 100644
--- a/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
+++ b/src/shaders/post_processing/gen5_6/Core_Kernels/PL_DNDI_ALG_UVCopy_NV12.asm
@@ -62,24 +62,29 @@
#include "DI_Hist_Save.asm"
////////////////////////////////////// Save the DN Curr Frame for Next Run ////////////////////////
- add (4) pCF_Y_OFFSET<1>:uw ubSRC_CF_OFFSET<4;4,1>:ub npDN_YUV:w
- // check top/bottom field first
- cmp.e.f0.0 (1) null<1>:w ubTFLD_FIRST<0;1,0>:ub 1:w
- (f0.0) jmpi (1) TOP_FIELD_FIRST
-
-BOTTOM_FIELD_FIRST:
- $for (0,0; <nY_NUM_OF_ROWS/2; 2,1) {
- mov (4) mudMSGHDR_DN(1,%1*4)<1> udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 2nd field luma from current frame (line 0,2)
- mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,4)<4;4,1> // 1st field luma from current frame (line 1,3)
- }
- jmpi (1) SAVE_DN_CURR
-
-TOP_FIELD_FIRST:
- $for (0,0; <nY_NUM_OF_ROWS/2; 2,1) {
- mov (4) mudMSGHDR_DN(1,%1*4)<1> udRESP(nDI_CURR_FRAME_LUMA_OFFSET+%2,0)<4;4,1> // 2nd field luma from current frame (line 0,2)
- mov (4) mudMSGHDR_DN(1,%1*4+4)<1> udRESP(nDI_CURR_2ND_FIELD_LUMA_OFFSET,%2*4)<4;4,1> // 1st field luma from current frame (line 1,3)
+ // previous frame
+ $for (0; <nY_NUM_OF_ROWS/2; 1) {
+ mov (16) mubMSGHDR_DN(1, %1*16)<1> ubRESP(nDI_PREV_FRAME_LUMA_OFFSET,%1*16)
}
-SAVE_DN_CURR:
+
+ mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
+ mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4)
+ mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
+ send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud
+
+ //Write UV through DATAPORT
+ mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
+ asr (1) rMSGSRC.1<1>:d rMSGSRC.1<0;1,0>:d 1:w // U/V block origin should be half of Y's
+ mov (1) rMSGSRC.2<1>:ud nDPR_BLOCK_SIZE_UV:ud // block width and height (16x2)
+ mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
+
+ mov (8) mubMSGHDR_DN(1, 0)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET, 1)<16 ;8,2>
+ mov (8) mubMSGHDR_DN(1, 1)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET, 16)<16 ;8,2>
+ mov (8) mubMSGHDR_DN(1, 16)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET+1, 1)<16 ;8,2>
+ mov (8) mubMSGHDR_DN(1, 17)<2> ubRESP(nDI_PREV_FRAME_CHROMA_OFFSET+1, 16)<16 ;8,2>
+ send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_UV:ud
+
+ // current frame
$for (0; <nY_NUM_OF_ROWS/2; 1) {
mov (16) mubMSGHDR_DN(1, %1*16)<1> ubRESP(nDI_CURR_FRAME_LUMA_OFFSET,%1*16)
}
@@ -87,7 +92,7 @@ SAVE_DN_CURR:
mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
mov (1) rMSGSRC.2<1>:ud nDPW_BLOCK_SIZE_DN:ud // block width and height (16x4)
mov (8) mudMSGHDR_DN(0)<1> rMSGSRC.0<8;8,1>:ud
- send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_Y:ud
+ send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nDPMW_MSG_LEN_PL_DN_DI+nBI_DESTINATION_1_Y:ud
//Write UV through DATAPORT
mov (2) rMSGSRC.0<1>:ud wORIX<2;2,1>:w // X origin and Y origin
@@ -99,4 +104,4 @@ SAVE_DN_CURR:
mov (8) mubMSGHDR_DN(1, 1)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET, 16)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 16)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 1)<16 ;8,2>
mov (8) mubMSGHDR_DN(1, 17)<2> ubRESP(nDI_CURR_FRAME_CHROMA_OFFSET+1, 16)<16 ;8,2>
- send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_UV:ud
\ No newline at end of file
+ send (8) dNULLREG mMSGHDR_DN udDUMMY_NULL nDATAPORT_WRITE nDPMW_MSGDSC+nMSGLEN_1+nBI_DESTINATION_1_UV:ud
diff --git a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5 b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
index 446fb4b..4563d20 100644
--- a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
+++ b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g4b.gen5
@@ -44,18 +44,23 @@
{ 0x00600001, 0x21a00022, 0x008d0100, 0x00000000 },
{ 0x00000001, 0x21c00022, 0x00000560, 0x00000000 },
{ 0x0d600031, 0x20000c04, 0x508d0000, 0x04082014 },
- { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 },
- { 0x01000010, 0x20003e2c, 0x0000003b, 0x00010001 },
- { 0x00010220, 0x34001c00, 0x00001400, 0x0000000a },
- { 0x00400001, 0x20400022, 0x00690580, 0x00000000 },
- { 0x00400001, 0x20500022, 0x006904d0, 0x00000000 },
- { 0x00400001, 0x20600022, 0x00690590, 0x00000000 },
- { 0x00400001, 0x20700022, 0x006904f0, 0x00000000 },
- { 0x00000220, 0x34001c00, 0x00001400, 0x00000008 },
- { 0x00400001, 0x20400022, 0x006904c0, 0x00000000 },
- { 0x00400001, 0x20500022, 0x00690580, 0x00000000 },
- { 0x00400001, 0x20600022, 0x006904e0, 0x00000000 },
- { 0x00400001, 0x20700022, 0x00690590, 0x00000000 },
+ { 0x00800001, 0x20400232, 0x00b10440, 0x00000000 },
+ { 0x00800001, 0x20500232, 0x00b10450, 0x00000000 },
+ { 0x00800001, 0x20600232, 0x00b10460, 0x00000000 },
+ { 0x00800001, 0x20700232, 0x00b10470, 0x00000000 },
+ { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
+ { 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
+ { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
+ { 0x01600031, 0x20000c04, 0x508d0000, 0x06082007 },
+ { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
+ { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
+ { 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
+ { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
+ { 0x00600001, 0x40400232, 0x00ae0481, 0x00000000 },
+ { 0x00600001, 0x40410232, 0x00ae0490, 0x00000000 },
+ { 0x00600001, 0x40500232, 0x00ae04a1, 0x00000000 },
+ { 0x00600001, 0x40510232, 0x00ae04b0, 0x00000000 },
+ { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 },
{ 0x00800001, 0x20400232, 0x00b104c0, 0x00000000 },
{ 0x00800001, 0x20500232, 0x00b104d0, 0x00000000 },
{ 0x00800001, 0x20600232, 0x00b104e0, 0x00000000 },
@@ -63,7 +68,7 @@
{ 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
{ 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
{ 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
- { 0x01600031, 0x20000c04, 0x508d0000, 0x06082007 },
+ { 0x01600031, 0x20000c04, 0x508d0000, 0x0608200a },
{ 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
{ 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
{ 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
@@ -72,7 +77,7 @@
{ 0x00600001, 0x40410232, 0x00ae0510, 0x00000000 },
{ 0x00600001, 0x40500232, 0x00ae0521, 0x00000000 },
{ 0x00600001, 0x40510232, 0x00ae0530, 0x00000000 },
- { 0x01600031, 0x20000c04, 0x508d0000, 0x04082008 },
+ { 0x01600031, 0x20000c04, 0x508d0000, 0x0408200b },
{ 0x01000040, 0x20863dad, 0x00000086, 0xffffffff },
{ 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 },
{ 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 },
@@ -81,10 +86,10 @@
{ 0x01000010, 0x20003dac, 0x00000086, 0x00010001 },
{ 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 },
{ 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 },
- { 0x00010220, 0x34001c00, 0x02001400, 0xffffff64 },
+ { 0x00010220, 0x34001c00, 0x02001400, 0xffffff5a },
{ 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 },
{ 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 },
- { 0x00000220, 0x34001c00, 0x00001400, 0xffffff5e },
+ { 0x00000220, 0x34001c00, 0x00001400, 0xffffff54 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 },
{ 0x0f000031, 0x20000c04, 0x708d0000, 0x82000000 },
diff --git a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
index 111d483..8d6ebe3 100644
--- a/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
+++ b/src/shaders/post_processing/gen5_6/nv12_dndi_nv12.g6b
@@ -117,18 +117,23 @@
{ 0x00600001, 0x21a00022, 0x008d0100, 0x00000000 },
{ 0x00000001, 0x21c00022, 0x00000560, 0x00000000 },
{ 0x05600031, 0x20000cc4, 0x000001a0, 0x04094014 },
- { 0x00400040, 0x22083e28, 0x00690024, 0x07000700 },
- { 0x01000010, 0x20003e2c, 0x0000003b, 0x00010001 },
- { 0x00010220, 0x34001c00, 0x00001400, 0x0000000a },
- { 0x00400001, 0x20400022, 0x00690580, 0x00000000 },
- { 0x00400001, 0x20500022, 0x006904d0, 0x00000000 },
- { 0x00400001, 0x20600022, 0x00690590, 0x00000000 },
- { 0x00400001, 0x20700022, 0x006904f0, 0x00000000 },
- { 0x00000220, 0x34001c00, 0x00001400, 0x00000008 },
- { 0x00400001, 0x20400022, 0x006904c0, 0x00000000 },
- { 0x00400001, 0x20500022, 0x00690580, 0x00000000 },
- { 0x00400001, 0x20600022, 0x006904e0, 0x00000000 },
- { 0x00400001, 0x20700022, 0x00690590, 0x00000000 },
+ { 0x00800001, 0x20400232, 0x00b10440, 0x00000000 },
+ { 0x00800001, 0x20500232, 0x00b10450, 0x00000000 },
+ { 0x00800001, 0x20600232, 0x00b10460, 0x00000000 },
+ { 0x00800001, 0x20700232, 0x00b10470, 0x00000000 },
+ { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
+ { 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
+ { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
+ { 0x05600031, 0x20000cc4, 0x00000020, 0x06094007 },
+ { 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
+ { 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
+ { 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
+ { 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
+ { 0x00600001, 0x40400232, 0x00ae0481, 0x00000000 },
+ { 0x00600001, 0x40410232, 0x00ae0490, 0x00000000 },
+ { 0x00600001, 0x40500232, 0x00ae04a1, 0x00000000 },
+ { 0x00600001, 0x40510232, 0x00ae04b0, 0x00000000 },
+ { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 },
{ 0x00800001, 0x20400232, 0x00b104c0, 0x00000000 },
{ 0x00800001, 0x20500232, 0x00b104d0, 0x00000000 },
{ 0x00800001, 0x20600232, 0x00b104e0, 0x00000000 },
@@ -136,7 +141,7 @@
{ 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
{ 0x00000001, 0x21080061, 0x00000000, 0x0003000f },
{ 0x00600001, 0x20200022, 0x008d0100, 0x00000000 },
- { 0x05600031, 0x20000cc4, 0x00000020, 0x06094007 },
+ { 0x05600031, 0x20000cc4, 0x00000020, 0x0609400a },
{ 0x00200001, 0x210001a1, 0x004500a0, 0x00000000 },
{ 0x0000000c, 0x21043ca5, 0x00000104, 0x00010001 },
{ 0x00000001, 0x21080061, 0x00000000, 0x0001000f },
@@ -145,7 +150,7 @@
{ 0x00600001, 0x40410232, 0x00ae0510, 0x00000000 },
{ 0x00600001, 0x40500232, 0x00ae0521, 0x00000000 },
{ 0x00600001, 0x40510232, 0x00ae0530, 0x00000000 },
- { 0x05600031, 0x20000cc4, 0x00000020, 0x04094008 },
+ { 0x05600031, 0x20000cc4, 0x00000020, 0x0409400b },
{ 0x01000040, 0x20863dad, 0x00000086, 0xffffffff },
{ 0x00000040, 0x20a03dad, 0x000000a0, 0x00100010 },
{ 0x05000010, 0x200035ac, 0x020000a0, 0x00000084 },
@@ -154,10 +159,10 @@
{ 0x01000010, 0x20003dac, 0x00000086, 0x00010001 },
{ 0x00010001, 0x20b80129, 0x000000c4, 0x00000000 },
{ 0x00010001, 0x20ba0231, 0x000000c6, 0x00000000 },
- { 0x00010220, 0x34001c00, 0x02001400, 0xffffff64 },
+ { 0x00010220, 0x34001c00, 0x02001400, 0xffffff5a },
{ 0x00000001, 0x20a001ad, 0x0000008a, 0x00000000 },
{ 0x00000040, 0x20a23dad, 0x000000a2, 0x00080008 },
- { 0x00000220, 0x34001c00, 0x00001400, 0xffffff5e },
+ { 0x00000220, 0x34001c00, 0x00001400, 0xffffff54 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x00600001, 0x21e00022, 0x008d0000, 0x00000000 },
{ 0x07000031, 0x20001cc4, 0x000001e0, 0x82000010 },
--
1.8.3.2
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