[Libva] [libva-intel-driver PATCH v2 2/10] support HEVC 10bits decoding
Xiang, Haihao
haihao.xiang at intel.com
Thu Dec 3 22:05:31 PST 2015
From: Peng Chen <peng.c.chen at intel.com>
v2: code cleanup
Signed-off-by: Peng Chen <peng.c.chen at intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
---
src/gen9_mfd.c | 61 ++++++++++++++++++++---
src/i965_decoder_utils.c | 21 +++++++-
src/i965_defines.h | 2 +
src/i965_device_info.c | 7 ++-
src/i965_drv_video.c | 127 +++++++++++++++++++++++++++++++++--------------
src/i965_drv_video.h | 2 +
6 files changed, 172 insertions(+), 48 deletions(-)
diff --git a/src/gen9_mfd.c b/src/gen9_mfd.c
index da76378..44b343f 100644
--- a/src/gen9_mfd.c
+++ b/src/gen9_mfd.c
@@ -109,6 +109,7 @@ gen9_hcpd_hevc_decode_init(VADriverContextP ctx,
VAPictureParameterBufferHEVC *pic_param;
struct object_surface *obj_surface;
uint32_t size;
+ int hevc_10bit = 0;
assert(decode_state->pic_param && decode_state->pic_param->buffer);
pic_param = (VAPictureParameterBufferHEVC *)decode_state->pic_param->buffer;
@@ -134,12 +135,22 @@ gen9_hcpd_hevc_decode_init(VADriverContextP ctx,
hevc_ensure_surface_bo(ctx, decode_state, obj_surface, pic_param);
gen9_hcpd_init_hevc_surface(ctx, pic_param, obj_surface, gen9_hcpd_context);
- size = ALIGN(gen9_hcpd_context->picture_width_in_pixels, 32) >> 3;
+ if((pic_param->bit_depth_luma_minus8 > 0)
+ || (pic_param->bit_depth_chroma_minus8 > 0))
+ hevc_10bit = 1;
+
+ if(hevc_10bit)
+ size = ALIGN(gen9_hcpd_context->picture_width_in_pixels, 32) >> 2;
+ else
+ size = ALIGN(gen9_hcpd_context->picture_width_in_pixels, 32) >> 3;
size <<= 6;
ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_line_buffer), "line buffer", size);
ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_tile_line_buffer), "tile line buffer", size);
- size = ALIGN(gen9_hcpd_context->picture_height_in_pixels + 6 * gen9_hcpd_context->picture_height_in_ctbs, 32) >> 3;
+ if(hevc_10bit)
+ size = ALIGN(gen9_hcpd_context->picture_height_in_pixels + 6 * gen9_hcpd_context->picture_height_in_ctbs, 32) >> 2;
+ else
+ size = ALIGN(gen9_hcpd_context->picture_height_in_pixels + 6 * gen9_hcpd_context->picture_height_in_ctbs, 32) >> 3;
size <<= 6;
ALLOC_GEN_BUFFER((&gen9_hcpd_context->deblocking_filter_tile_column_buffer), "tile column buffer", size);
@@ -158,15 +169,24 @@ gen9_hcpd_hevc_decode_init(VADriverContextP ctx,
size <<= 6;
ALLOC_GEN_BUFFER((&gen9_hcpd_context->metadata_tile_column_buffer), "metadata tile column buffer", size);
- size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 3 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 3;
+ if(hevc_10bit)
+ size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 3 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 2;
+ else
+ size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 3 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 3;
size <<= 6;
ALLOC_GEN_BUFFER((&gen9_hcpd_context->sao_line_buffer), "sao line buffer", size);
- size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 3;
+ if(hevc_10bit)
+ size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 2;
+ else
+ size = ALIGN(((gen9_hcpd_context->picture_width_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_width_in_ctbs), 16) >> 3;
size <<= 6;
ALLOC_GEN_BUFFER((&gen9_hcpd_context->sao_tile_line_buffer), "sao tile line buffer", size);
- size = ALIGN(((gen9_hcpd_context->picture_height_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_height_in_ctbs), 16) >> 3;
+ if(hevc_10bit)
+ size = ALIGN(((gen9_hcpd_context->picture_height_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_height_in_ctbs), 16) >> 2;
+ else
+ size = ALIGN(((gen9_hcpd_context->picture_height_in_pixels >> 1) + 6 * gen9_hcpd_context->picture_height_in_ctbs), 16) >> 3;
size <<= 6;
ALLOC_GEN_BUFFER((&gen9_hcpd_context->sao_tile_column_buffer), "sao tile column buffer", size);
@@ -208,9 +228,11 @@ gen9_hcpd_surface_state(VADriverContextP ctx,
struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
struct object_surface *obj_surface = decode_state->render_object;
unsigned int y_cb_offset;
+ VAPictureParameterBufferHEVC *pic_param;
assert(obj_surface);
+ pic_param = (VAPictureParameterBufferHEVC *)decode_state->pic_param->buffer;
y_cb_offset = obj_surface->y_cb_offset;
BEGIN_BCS_BATCH(batch, 3);
@@ -219,9 +241,19 @@ gen9_hcpd_surface_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch,
(0 << 28) | /* surface id */
(obj_surface->width - 1)); /* pitch - 1 */
- OUT_BCS_BATCH(batch,
+ if((pic_param->bit_depth_luma_minus8 > 0)
+ || (pic_param->bit_depth_chroma_minus8 > 0))
+ {
+ OUT_BCS_BATCH(batch,
+ (SURFACE_FORMAT_P010 << 28) |
+ y_cb_offset);
+ }
+ else
+ {
+ OUT_BCS_BATCH(batch,
(SURFACE_FORMAT_PLANAR_420_8 << 28) |
y_cb_offset);
+ }
ADVANCE_BCS_BATCH(batch);
}
@@ -466,6 +498,8 @@ gen9_hcpd_pic_state(VADriverContextP ctx,
pic_param->slice_parsing_fields.bits.sample_adaptive_offset_enabled_flag << 3 |
0);
OUT_BCS_BATCH(batch,
+ pic_param->bit_depth_luma_minus8 << 27 |
+ pic_param->bit_depth_chroma_minus8 << 24 |
pcm_sample_bit_depth_luma_minus1 << 20 |
pcm_sample_bit_depth_chroma_minus1 << 16 |
pic_param->max_transform_hierarchy_depth_inter << 13 |
@@ -760,6 +794,7 @@ gen9_hcpd_slice_state(VADriverContextP ctx,
struct intel_batchbuffer *batch = gen9_hcpd_context->base.batch;
int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
unsigned short collocated_ref_idx, collocated_from_l0_flag;
+ int sliceqp_sign_flag = 0, sliceqp = 0;
slice_hor_pos = slice_param->slice_segment_address % gen9_hcpd_context->picture_width_in_ctbs;
slice_ver_pos = slice_param->slice_segment_address / gen9_hcpd_context->picture_width_in_ctbs;
@@ -791,6 +826,17 @@ gen9_hcpd_slice_state(VADriverContextP ctx,
collocated_from_l0_flag = gen9_hcpd_context->first_inter_slice_collocated_from_l0_flag;
}
+ sliceqp = pic_param->init_qp_minus26 + 26 + slice_param->slice_qp_delta;
+ if((pic_param->bit_depth_luma_minus8 > 0)
+ || (pic_param->bit_depth_chroma_minus8 > 0))
+ {
+ if(sliceqp < 0)
+ {
+ sliceqp_sign_flag = 1;
+ sliceqp = -sliceqp;
+ }
+ }
+
BEGIN_BCS_BATCH(batch, 9);
OUT_BCS_BATCH(batch, HCP_SLICE_STATE | (9 - 2));
@@ -804,9 +850,10 @@ gen9_hcpd_slice_state(VADriverContextP ctx,
OUT_BCS_BATCH(batch,
(slice_param->slice_cr_qp_offset & 0x1f) << 17 |
(slice_param->slice_cb_qp_offset & 0x1f) << 12 |
- (pic_param->init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 6 |
+ sliceqp << 6 |
slice_param->LongSliceFlags.fields.slice_temporal_mvp_enabled_flag << 5 |
slice_param->LongSliceFlags.fields.dependent_slice_segment_flag << 4 |
+ sliceqp_sign_flag << 3 |
!next_slice_param << 2 |
slice_param->LongSliceFlags.fields.slice_type);
OUT_BCS_BATCH(batch,
diff --git a/src/i965_decoder_utils.c b/src/i965_decoder_utils.c
index 3085a56..53a5aa1 100644
--- a/src/i965_decoder_utils.c
+++ b/src/i965_decoder_utils.c
@@ -1121,9 +1121,26 @@ hevc_ensure_surface_bo(
)
{
VAStatus va_status = VA_STATUS_SUCCESS;
+ int update = 0;
+ unsigned int fourcc = VA_FOURCC_NV12;
+
+ if((pic_param->bit_depth_luma_minus8 > 0)
+ || (pic_param->bit_depth_chroma_minus8 > 0))
+ {
+ if(obj_surface->fourcc != VA_FOURCC_P010)
+ {
+ update = 1;
+ fourcc = VA_FOURCC_P010;
+ }
+ }
+ else if(obj_surface->fourcc != VA_FOURCC_NV12)
+ {
+ update = 1;
+ fourcc = VA_FOURCC_NV12;
+ }
/* (Re-)allocate the underlying surface buffer store, if necessary */
- if (!obj_surface->bo || obj_surface->fourcc != VA_FOURCC_NV12) {
+ if (!obj_surface->bo || update) {
struct i965_driver_data * const i965 = i965_driver_data(ctx);
i965_destroy_surface_storage(obj_surface);
@@ -1131,7 +1148,7 @@ hevc_ensure_surface_bo(
va_status = i965_check_alloc_surface_bo(ctx,
obj_surface,
i965->codec_info->has_tiled_surface,
- VA_FOURCC_NV12,
+ fourcc,
SUBSAMPLE_YUV420);
}
diff --git a/src/i965_defines.h b/src/i965_defines.h
index 86a3725..65c0b11 100755
--- a/src/i965_defines.h
+++ b/src/i965_defines.h
@@ -797,6 +797,8 @@
#define SURFACE_FORMAT_R8B8_UNORM 10
#define SURFACE_FORMAT_R8_UNORM 11
#define SURFACE_FORMAT_Y8_UNORM 12
+#define SURFACE_FORMAT_P010 13
+#define SURFACE_FORMAT_P016 14
#define AVS_FILTER_ADAPTIVE_8_TAP 0
#define AVS_FILTER_NEAREST 1
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index a844374..db904ae 100644
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -44,7 +44,10 @@
/* Extra set of chroma formats supported for JPEG encoding (beyond YUV 4:2:0) */
#define EXTRA_JPEG_ENC_CHROMA_FORMATS \
(VA_RT_FORMAT_YUV400| VA_RT_FORMAT_YUV422 | VA_RT_FORMAT_YUV444 | VA_RT_FORMAT_RGB32)
-
+
+#define EXTRA_HEVC_DEC_CHROMA_FORMATS \
+ (VA_RT_FORMAT_YUV420_10BPP)
+
/* Defines VA profile as a 32-bit unsigned integer mask */
#define VA_PROFILE_MASK(PROFILE) \
(1U << VAProfile##PROFILE)
@@ -377,6 +380,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
.h264_dec_chroma_formats = EXTRA_H264_DEC_CHROMA_FORMATS,
.jpeg_dec_chroma_formats = EXTRA_JPEG_DEC_CHROMA_FORMATS,
.jpeg_enc_chroma_formats = EXTRA_JPEG_ENC_CHROMA_FORMATS,
+ .hevc_dec_chroma_formats = EXTRA_HEVC_DEC_CHROMA_FORMATS,
.has_mpeg2_decoding = 1,
.has_h264_decoding = 1,
@@ -395,6 +399,7 @@ static struct hw_codec_info bxt_hw_codec_info = {
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
.has_hevc_encoding = 1,
+ .has_hevc10_decoding = 1,
.num_filters = 5,
.filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 54c7030..e52e982 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -106,6 +106,9 @@
#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding && \
(ctx)->intel.has_bsd)
+#define HAS_HEVC10_DECODING(ctx) ((ctx)->codec_info->has_hevc10_decoding && \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -141,6 +144,8 @@ static int get_sampling_from_fourcc(unsigned int fourcc);
#define I_YV12 2, 2, 3, {I965_8BITS, I965_2BITS, I965_2BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_2, OFFSET_0}, {PLANE_1, OFFSET_0} }
#define I_IMC1 I_YV12
+#define I_P010 2, 2, 2, {I965_16BITS, I965_8BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_1, OFFSET_0}, {PLANE_1, OFFSET_16} }
+
#define I_422H 2, 1, 3, {I965_8BITS, I965_4BITS, I965_4BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_1, OFFSET_0}, {PLANE_2, OFFSET_0} }
#define I_422V 1, 2, 3, {I965_8BITS, I965_4BITS, I965_4BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_1, OFFSET_0}, {PLANE_2, OFFSET_0} }
#define I_YV16 2, 1, 3, {I965_8BITS, I965_4BITS, I965_4BITS}, 3, { {PLANE_0, OFFSET_0}, {PLANE_2, OFFSET_0}, {PLANE_1, OFFSET_0} }
@@ -185,6 +190,8 @@ static const i965_fourcc_info i965_fourcc_infos[] = {
DEF_YUV(YV12, YUV420, I_SI),
DEF_YUV(IMC1, YUV420, I_S),
+ DEF_YUV(P010, YUV420, I_SI),
+
DEF_YUV(422H, YUV422H, I_SI),
DEF_YUV(422V, YUV422V, I_S),
DEF_YUV(YV16, YUV422H, I_S),
@@ -580,6 +587,10 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileHEVCMain;
}
+ if (HAS_HEVC10_DECODING(i965)) {
+ profile_list[i++] = VAProfileHEVCMain10;
+ }
+
if (i965->wrapper_pdrvctx) {
VAProfile wrapper_list[4];
int wrapper_num;
@@ -683,6 +694,12 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
break;
+ case VAProfileHEVCMain10:
+ if (HAS_HEVC10_DECODING(i965))
+ entrypoint_list[n++] = VAEntrypointVLD;
+
+ break;
+
case VAProfileVP9Profile0:
if (i965->wrapper_pdrvctx) {
VAStatus va_status = VA_STATUS_SUCCESS;
@@ -794,6 +811,14 @@ i965_validate_config(VADriverContextP ctx, VAProfile profile,
break;
+ case VAProfileHEVCMain10:
+ if (HAS_HEVC10_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+ va_status = VA_STATUS_SUCCESS;
+ else
+ va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
+
+ break;
+
case VAProfileVP9Profile0:
if (i965->wrapper_pdrvctx)
va_status = VA_STATUS_SUCCESS;
@@ -834,9 +859,13 @@ i965_get_default_chroma_formats(VADriverContextP ctx, VAProfile profile,
chroma_formats |= i965->codec_info->jpeg_dec_chroma_formats;
if (HAS_JPEG_ENCODING(i965) && entrypoint == VAEntrypointEncPicture)
chroma_formats |= i965->codec_info->jpeg_enc_chroma_formats;
-
break;
+ case VAProfileHEVCMain10:
+ chroma_formats = 0; // clear YUV420 8bits format support
+ if (HAS_HEVC10_DECODING(i965) && entrypoint == VAEntrypointVLD)
+ chroma_formats |= i965->codec_info->hevc_dec_chroma_formats;
+ break;
default:
break;
}
@@ -1197,6 +1226,7 @@ i965_suface_external_memory(VADriverContextP ctx,
switch (obj_surface->fourcc) {
case VA_FOURCC_NV12:
+ case VA_FOURCC_P010:
ASSERT_RET(memory_attibute->num_planes == 2, VA_STATUS_ERROR_INVALID_PARAMETER);
ASSERT_RET(memory_attibute->pitches[0] == memory_attibute->pitches[1], VA_STATUS_ERROR_INVALID_PARAMETER);
@@ -1424,6 +1454,7 @@ i965_CreateSurfaces2(
/* support 420 & 422 & RGB32 format, 422 and RGB32 are only used
* for post-processing (including color conversion) */
if (VA_RT_FORMAT_YUV420 != format &&
+ VA_RT_FORMAT_YUV420_10BPP != format &&
VA_RT_FORMAT_YUV422 != format &&
VA_RT_FORMAT_YUV444 != format &&
VA_RT_FORMAT_YUV411 != format &&
@@ -1488,10 +1519,10 @@ i965_CreateSurfaces2(
if (memory_attibute->pitches[0]) {
int bpp_1stplane = bpp_1stplane_by_fourcc(expected_fourcc);
ASSERT_RET(bpp_1stplane, VA_STATUS_ERROR_INVALID_PARAMETER);
- obj_surface->width = memory_attibute->pitches[0]/bpp_1stplane;
+ obj_surface->width = memory_attibute->pitches[0];
obj_surface->user_h_stride_set = true;
ASSERT_RET(IS_ALIGNED(obj_surface->width, 16), VA_STATUS_ERROR_INVALID_PARAMETER);
- ASSERT_RET(obj_surface->width >= width, VA_STATUS_ERROR_INVALID_PARAMETER);
+ ASSERT_RET(obj_surface->width >= width * bpp_1stplane, VA_STATUS_ERROR_INVALID_PARAMETER);
if (memory_attibute->offsets[1]) {
ASSERT_RET(!memory_attibute->offsets[0], VA_STATUS_ERROR_INVALID_PARAMETER);
@@ -3086,7 +3117,7 @@ i965_encoder_render_picture(VADriverContextP ctx,
if ((param->type == VAEncPackedHeaderRawData) ||
(param->type == VAEncPackedHeaderSlice)) {
vaStatus = I965_RENDER_ENCODE_BUFFER(packed_header_params_ext);
- } else if((obj_config->profile == VAProfileHEVCMain)&&
+ } else if((obj_config->profile == VAProfileHEVCMain) &&
(encode->last_packed_header_type == VAEncPackedHeaderSequence)) {
vaStatus = i965_encoder_render_packed_header_parameter_buffer(ctx,
obj_context,
@@ -3180,7 +3211,7 @@ i965_encoder_render_picture(VADriverContextP ctx,
((encode->last_packed_header_type & (~VAEncPackedHeaderMiscMask)) != 0)),
VA_STATUS_ERROR_ENCODING_ERROR);
- if((obj_config->profile == VAProfileHEVCMain)&&
+ if((obj_config->profile == VAProfileHEVCMain) &&
(encode->last_packed_header_type == VAEncPackedHeaderSequence)) {
vaStatus = i965_encoder_render_packed_header_data_buffer(ctx,
@@ -3774,25 +3805,29 @@ i965_check_alloc_surface_bo(VADriverContextP ctx,
obj_surface->x_cb_offset = 0; /* X offset is always 0 */
obj_surface->x_cr_offset = 0;
+ int bpp_1stplane = bpp_1stplane_by_fourcc(fourcc);
+
+ if (obj_surface->user_h_stride_set) {
+ ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
+ } else
+ obj_surface->width = ALIGN(obj_surface->orig_width * bpp_1stplane, 128);
+
+ if (obj_surface->user_v_stride_set) {
+ ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
+ } else
+ obj_surface->height = ALIGN(obj_surface->orig_height, 32);
+
if ((tiled && !obj_surface->user_disable_tiling)) {
ASSERT_RET(fourcc != VA_FOURCC_I420 &&
fourcc != VA_FOURCC_IYUV &&
fourcc != VA_FOURCC_YV12,
VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT);
- if (obj_surface->user_h_stride_set) {
- ASSERT_RET(IS_ALIGNED(obj_surface->width, 128), VA_STATUS_ERROR_INVALID_PARAMETER);
- } else
- obj_surface->width = ALIGN(obj_surface->orig_width, 128);
-
- if (obj_surface->user_v_stride_set) {
- ASSERT_RET(IS_ALIGNED(obj_surface->height, 32), VA_STATUS_ERROR_INVALID_PARAMETER);
- } else
- obj_surface->height = ALIGN(obj_surface->orig_height, 32);
region_height = obj_surface->height;
switch (fourcc) {
case VA_FOURCC_NV12:
+ case VA_FOURCC_P010:
assert(subsampling == SUBSAMPLE_YUV420);
obj_surface->cb_cr_pitch = obj_surface->width;
obj_surface->cb_cr_width = obj_surface->orig_width / 2;
@@ -3929,6 +3964,7 @@ i965_check_alloc_surface_bo(VADriverContextP ctx,
switch (fourcc) {
case VA_FOURCC_NV12:
+ case VA_FOURCC_P010:
obj_surface->y_cb_offset = obj_surface->height;
obj_surface->y_cr_offset = obj_surface->height;
obj_surface->cb_cr_width = obj_surface->orig_width / 2;
@@ -4103,6 +4139,7 @@ VAStatus i965_DeriveImage(VADriverContextP ctx,
break;
case VA_FOURCC_NV12:
+ case VA_FOURCC_P010:
image->num_planes = 2;
image->pitches[0] = w_pitch; /* Y */
image->offsets[0] = 0;
@@ -5439,7 +5476,13 @@ i965_QuerySurfaceAttributes(VADriverContextP ctx,
attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
attribs[i].value.value.i = VA_FOURCC_444P;
i++;
- } else {
+ } else if (obj_config->profile == VAProfileHEVCMain10) {
+ attribs[i].type = VASurfaceAttribPixelFormat;
+ attribs[i].value.type = VAGenericValueTypeInteger;
+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+ attribs[i].value.value.i = VA_FOURCC_P010;
+ i++;
+ } else {
attribs[i].type = VASurfaceAttribPixelFormat;
attribs[i].value.type = VAGenericValueTypeInteger;
attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
@@ -5565,29 +5608,37 @@ i965_QuerySurfaceAttributes(VADriverContextP ctx,
} else if (obj_config->entrypoint == VAEntrypointEncSlice || /* encode */
obj_config->entrypoint == VAEntrypointVideoProc) { /* vpp */
- attribs[i].type = VASurfaceAttribPixelFormat;
- attribs[i].value.type = VAGenericValueTypeInteger;
- attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
- attribs[i].value.value.i = VA_FOURCC_NV12;
- i++;
-
- attribs[i].type = VASurfaceAttribPixelFormat;
- attribs[i].value.type = VAGenericValueTypeInteger;
- attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
- attribs[i].value.value.i = VA_FOURCC_I420;
- i++;
-
- attribs[i].type = VASurfaceAttribPixelFormat;
- attribs[i].value.type = VAGenericValueTypeInteger;
- attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
- attribs[i].value.value.i = VA_FOURCC_YV12;
- i++;
-
- attribs[i].type = VASurfaceAttribPixelFormat;
- attribs[i].value.type = VAGenericValueTypeInteger;
- attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
- attribs[i].value.value.i = VA_FOURCC_IMC3;
- i++;
+ if (obj_config->profile == VAProfileHEVCMain10) {
+ attribs[i].type = VASurfaceAttribPixelFormat;
+ attribs[i].value.type = VAGenericValueTypeInteger;
+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+ attribs[i].value.value.i = VA_FOURCC_P010;
+ i++;
+ } else {
+ attribs[i].type = VASurfaceAttribPixelFormat;
+ attribs[i].value.type = VAGenericValueTypeInteger;
+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+ attribs[i].value.value.i = VA_FOURCC_NV12;
+ i++;
+
+ attribs[i].type = VASurfaceAttribPixelFormat;
+ attribs[i].value.type = VAGenericValueTypeInteger;
+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+ attribs[i].value.value.i = VA_FOURCC_I420;
+ i++;
+
+ attribs[i].type = VASurfaceAttribPixelFormat;
+ attribs[i].value.type = VAGenericValueTypeInteger;
+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+ attribs[i].value.value.i = VA_FOURCC_YV12;
+ i++;
+
+ attribs[i].type = VASurfaceAttribPixelFormat;
+ attribs[i].value.type = VAGenericValueTypeInteger;
+ attribs[i].flags = VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE;
+ attribs[i].value.value.i = VA_FOURCC_IMC3;
+ i++;
+ }
if (obj_config->entrypoint == VAEntrypointVideoProc) {
attribs[i].type = VASurfaceAttribPixelFormat;
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index f688ec2..44983da 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -365,6 +365,7 @@ struct hw_codec_info
unsigned int h264_dec_chroma_formats;
unsigned int jpeg_dec_chroma_formats;
unsigned int jpeg_enc_chroma_formats;
+ unsigned int hevc_dec_chroma_formats;
unsigned int has_mpeg2_decoding:1;
unsigned int has_mpeg2_encoding:1;
@@ -385,6 +386,7 @@ struct hw_codec_info
unsigned int has_h264_mvc_encoding:1;
unsigned int has_hevc_decoding:1;
unsigned int has_hevc_encoding:1;
+ unsigned int has_hevc10_decoding:1;
unsigned int num_filters;
struct i965_filter filters[VAProcFilterCount];
--
1.9.1
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