[Libva] [PATCH 18/18] Encoding: Add the support of ROI under CQP on Haswell/Ivybridge
Zhao, Yakui
yakui.zhao at intel.com
Mon Jan 12 05:01:41 PST 2015
From: Zhao Yakui <yakui.zhao at intel.com>
The Broadwell support will be added later as it needs the update of
GPU shader for encoding.
Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
---
src/gen6_mfc_common.c | 28 ++++++++++++++++++++++++++++
src/i965_drv_video.c | 14 ++++++++++++++
src/i965_encoder.c | 6 ++++++
3 files changed, 48 insertions(+)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 083fdbe..7ef626e 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1795,6 +1795,8 @@ intel_h264_enc_roi_config(VADriverContextP ctx,
int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
+ int row_start, row_end, col_start, col_end;
+
vme_context->roi_enabled = 0;
encoder_context->soft_batch_force = 0;
/* Restriction: Disable ROI when multi-slice is enabled */
@@ -1845,6 +1847,32 @@ intel_h264_enc_roi_config(VADriverContextP ctx,
qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
memset(vme_context->qp_per_mb, qp, width_in_mbs * height_in_mbs);
+
+ for (j = pParamROI->num_roi; j ; j--) {
+ int qp_delta, qp_clip;
+
+ region_roi = (VAEncROI *)pParamROI->roi + j - 1;
+
+ col_start = region_roi->roi_rectangle.x;
+ col_end = col_start + region_roi->roi_rectangle.width;
+ row_start = region_roi->roi_rectangle.y;
+ row_end = row_start + region_roi->roi_rectangle.height;
+
+ col_start = col_start / 16;
+ col_end = (col_end + 15) / 16;
+ row_start = row_start / 16;
+ row_end = (row_end + 15) / 16;
+
+ qp_delta = region_roi->roi_value;
+ qp_clip = qp + qp_delta;
+
+ BRC_CLIP(qp_clip, 1, 51);
+
+ for (i = row_start; i < row_end; i++) {
+ qp_ptr = vme_context->qp_per_mb + (i * width_in_mbs) + col_start;
+ memset(qp_ptr, qp_clip, (col_end - col_start));
+ }
+ }
} else {
/*
* TODO: Disable it for non CBR-CQP.
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 5a61bde..fc7040f 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -776,6 +776,20 @@ i965_GetConfigAttributes(VADriverContextP ctx,
attrib_list[i].value = VA_DEC_SLICE_MODE_NORMAL;
break;
+ case VAConfigAttribEncROI:
+ if ((entrypoint == VAEntrypointEncSlice) &&
+ HAS_H264_ENCODING(i965) &&
+ (profile == VAProfileH264ConstrainedBaseline ||
+ profile == VAProfileH264Main ||
+ profile == VAProfileH264High) &&
+ (IS_GEN7(i965->intel.device_info))) {
+ VAConfigAttribValEncROI *roi_config = (VAConfigAttribValEncROI *)&(attrib_list[i].value);
+ roi_config->bits.num_roi_regions = 1;
+ roi_config->bits.roi_rc_priority_support = 1;
+ break;
+ }
+ break;
+
default:
/* Do nothing */
attrib_list[i].value = VA_ATTRIB_NOT_SUPPORTED;
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index b88c64e..bc7b2a9 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -577,6 +577,12 @@ intel_enc_hw_context_init(VADriverContextP ctx,
}
}
+ if ((encoder_context->rate_control_mode == VA_RC_CBR) &&
+ encoder_context->context_roi) {
+ WARN_ONCE("ROI is not supported under CBR. It will be added later\n");
+ encoder_context->context_roi = 0;
+ }
+
vme_context_init(ctx, encoder_context);
if(obj_config->profile != VAProfileJPEGBaseline) {
assert(encoder_context->vme_context);
--
1.7.10.1
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