[Libva] [PATCH 13/14] scaling matrix of h264 encoder on gen8/gen9
Zhao Yakui
yakui.zhao at intel.com
Wed Jul 6 08:40:53 UTC 2016
On 06/30/2016 10:33 AM, Pengfei Qu wrote:
> From: Jia Meng<jia.meng at intel.com>
>
> qm is in raster scan order per va api, and fqm is in
> column wise raster scan order per hardware requirement.
The title is inconsistent with what is done.
Can we remove it for gen6/gen7/gen75 and only keep it for gen8/gen9?
Thanks
Yakui
>
> Signed-off-by: Jia Meng<jia.meng at intel.com>
> Signed-off-by: Pengfei Qu<Pengfei.Qu at intel.com>
> ---
> src/gen6_mfc.c | 12 ++++--
> src/gen6_mfc.h | 2 +
> src/gen75_mfc.c | 12 ++++--
> src/gen7_mfc.c | 8 +++-
> src/gen8_mfc.c | 122 ++++++++++++++++++++++++++++++++++++++++-------------
> src/gen9_mfc.c | 127 ++++++++++++++++++++++++++++++++++++++++++--------------
> 6 files changed, 211 insertions(+), 72 deletions(-)
>
> diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c
> index b482712..e9e76cb 100644
> --- a/src/gen6_mfc.c
> +++ b/src/gen6_mfc.c
> @@ -464,7 +464,9 @@ gen6_mfc_avc_slice_state(VADriverContextP ctx,
> ADVANCE_BCS_BATCH(batch);
> }
>
> -static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> struct intel_batchbuffer *batch = encoder_context->base.batch;
> int i;
> @@ -480,7 +482,9 @@ static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_con
> ADVANCE_BCS_BATCH(batch);
> }
>
> -static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> struct intel_batchbuffer *batch = encoder_context->base.batch;
> int i;
> @@ -639,8 +643,8 @@ static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
> gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
> gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
> mfc_context->avc_img_state(ctx, encode_state, encoder_context);
> - mfc_context->avc_qm_state(ctx, encoder_context);
> - mfc_context->avc_fqm_state(ctx, encoder_context);
> + mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
> + mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
> gen6_mfc_avc_directmode_state(ctx, encoder_context);
> intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
> }
> diff --git a/src/gen6_mfc.h b/src/gen6_mfc.h
> index fa610d4..4561d43 100644
> --- a/src/gen6_mfc.h
> +++ b/src/gen6_mfc.h
> @@ -319,8 +319,10 @@ struct gen6_mfc_context
> struct encode_state *encode_state,
> struct intel_encoder_context *encoder_context);
> void (*avc_qm_state)(VADriverContextP ctx,
> + struct encode_state *encode_state,
> struct intel_encoder_context *encoder_context);
> void (*avc_fqm_state)(VADriverContextP ctx,
> + struct encode_state *encode_state,
> struct intel_encoder_context *encoder_context);
> void (*insert_object)(VADriverContextP ctx,
> struct intel_encoder_context *encoder_context,
> diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c
> index f69a186..838d0d8 100644
> --- a/src/gen75_mfc.c
> +++ b/src/gen75_mfc.c
> @@ -331,7 +331,9 @@ gen75_mfc_qm_state(VADriverContextP ctx,
> }
>
> static void
> -gen75_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen75_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> unsigned int qm[16] = {
> 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> @@ -368,7 +370,9 @@ gen75_mfc_fqm_state(VADriverContextP ctx,
> }
>
> static void
> -gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen75_mfc_avc_fqm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> unsigned int qm[32] = {
> 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> @@ -827,8 +831,8 @@ static void gen75_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
> gen75_mfc_pipe_buf_addr_state(ctx, encoder_context);
> gen75_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
> mfc_context->avc_img_state(ctx, encode_state, encoder_context);
> - mfc_context->avc_qm_state(ctx, encoder_context);
> - mfc_context->avc_fqm_state(ctx, encoder_context);
> + mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
> + mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
> gen75_mfc_avc_directmode_state(ctx, encoder_context);
> intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
> }
> diff --git a/src/gen7_mfc.c b/src/gen7_mfc.c
> index 2c17779..ce43e90 100644
> --- a/src/gen7_mfc.c
> +++ b/src/gen7_mfc.c
> @@ -287,7 +287,9 @@ gen7_mfc_qm_state(VADriverContextP ctx,
> }
>
> static void
> -gen7_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen7_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> unsigned int qm[16] = {
> 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> @@ -324,7 +326,9 @@ gen7_mfc_fqm_state(VADriverContextP ctx,
> }
>
> static void
> -gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen7_mfc_avc_fqm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> unsigned int qm[32] = {
> 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> diff --git a/src/gen8_mfc.c b/src/gen8_mfc.c
> index 186bb9b..c252c1a 100644
> --- a/src/gen8_mfc.c
> +++ b/src/gen8_mfc.c
> @@ -129,6 +129,23 @@ static struct i965_kernel gen9_mfc_kernels[] = {
> },
> };
>
> +static const uint32_t qm_flat[16] = {
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010
> +};
> +
> +static const uint32_t fqm_flat[32] = {
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000
> +};
>
> #define INTER_MODE_MASK 0x03
> #define INTER_8X8 0x03
> @@ -361,7 +378,7 @@ gen8_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
> static void
> gen8_mfc_qm_state(VADriverContextP ctx,
> int qm_type,
> - unsigned int *qm,
> + const uint32_t *qm,
> int qm_length,
> struct intel_encoder_context *encoder_context)
> {
> @@ -380,25 +397,42 @@ gen8_mfc_qm_state(VADriverContextP ctx,
> }
>
> static void
> -gen8_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen8_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> - unsigned int qm[16] = {
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010
> - };
> + const unsigned int *qm_4x4_intra;
> + const unsigned int *qm_4x4_inter;
> + const unsigned int *qm_8x8_intra;
> + const unsigned int *qm_8x8_inter;
> + VAEncSequenceParameterBufferH264 *pSeqParameter =
> + (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
> + VAEncPictureParameterBufferH264 *pPicParameter =
> + (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
> +
> + if (!pSeqParameter->seq_fields.bits.seq_scaling_matrix_present_flag
> +&& !pPicParameter->pic_fields.bits.pic_scaling_matrix_present_flag) {
> + qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
> + } else {
> + VAIQMatrixBufferH264 *qm;
> + assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
> + qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
> + qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
> + qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
> + qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
> + qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
> + }
>
> - gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
> - gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
> - gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
> - gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
> + gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
> + gen8_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
> + gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
> + gen8_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
> }
>
> static void
> gen8_mfc_fqm_state(VADriverContextP ctx,
> int fqm_type,
> - unsigned int *fqm,
> + const uint32_t *fqm,
> int fqm_length,
> struct intel_encoder_context *encoder_context)
> {
> @@ -417,23 +451,51 @@ gen8_mfc_fqm_state(VADriverContextP ctx,
> }
>
> static void
> -gen8_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen8_mfc_avc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
> {
> - unsigned int qm[32] = {
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000
> - };
> + int i, j;
> + for (i = 0; i< len; i++)
> + for (j = 0; j< len; j++)
> + fqm[i * len + j] = (1<< 16) / qm[j * len + i];
> +}
>
> - gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
> - gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
> - gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
> - gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
> +static void
> +gen8_mfc_avc_fqm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> +{
> + VAEncSequenceParameterBufferH264 *pSeqParameter =
> + (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
> + VAEncPictureParameterBufferH264 *pPicParameter =
> + (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
> +
> + if (!pSeqParameter->seq_fields.bits.seq_scaling_matrix_present_flag
> +&& !pPicParameter->pic_fields.bits.pic_scaling_matrix_present_flag) {
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
> + } else {
> + int i;
> + uint32_t fqm[32];
> + VAIQMatrixBufferH264 *qm;
> + assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
> + qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
> +
> + for (i = 0; i< 3; i++)
> + gen8_mfc_avc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
> +
> + for (i = 3; i< 6; i++)
> + gen8_mfc_avc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
> +
> + gen8_mfc_avc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
> +
> + gen8_mfc_avc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
> + gen8_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
> + }
> }
>
> static void
> @@ -768,8 +830,8 @@ static void gen8_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
> gen8_mfc_pipe_buf_addr_state(ctx, encoder_context);
> gen8_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
> mfc_context->avc_img_state(ctx, encode_state, encoder_context);
> - mfc_context->avc_qm_state(ctx, encoder_context);
> - mfc_context->avc_fqm_state(ctx, encoder_context);
> + mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
> + mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
> gen8_mfc_avc_directmode_state(ctx, encoder_context);
> intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
> }
> diff --git a/src/gen9_mfc.c b/src/gen9_mfc.c
> index 109e697..87b118f 100644
> --- a/src/gen9_mfc.c
> +++ b/src/gen9_mfc.c
> @@ -76,6 +76,24 @@ static struct i965_kernel gen9_mfc_kernels[] = {
> },
> };
>
> +static const uint32_t qm_flat[16] = {
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> + 0x10101010, 0x10101010, 0x10101010, 0x10101010
> +};
> +
> +static const uint32_t fqm_flat[32] = {
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> + 0x10001000, 0x10001000, 0x10001000, 0x10001000
> +};
> +
> #define INTER_MODE_MASK 0x03
> #define INTER_8X8 0x03
> #define INTER_16X8 0x01
> @@ -286,7 +304,7 @@ gen9_mfc_avc_img_state(VADriverContextP ctx, struct encode_state *encode_state,
> static void
> gen9_mfc_qm_state(VADriverContextP ctx,
> int qm_type,
> - unsigned int *qm,
> + const uint32_t *qm,
> int qm_length,
> struct intel_encoder_context *encoder_context)
> {
> @@ -305,25 +323,42 @@ gen9_mfc_qm_state(VADriverContextP ctx,
> }
>
> static void
> -gen9_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen9_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> - unsigned int qm[16] = {
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010,
> - 0x10101010, 0x10101010, 0x10101010, 0x10101010
> - };
> -
> - gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, encoder_context);
> - gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, encoder_context);
> - gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, encoder_context);
> - gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, encoder_context);
> + const unsigned int *qm_4x4_intra;
> + const unsigned int *qm_4x4_inter;
> + const unsigned int *qm_8x8_intra;
> + const unsigned int *qm_8x8_inter;
> + VAEncSequenceParameterBufferH264 *pSeqParameter =
> + (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
> + VAEncPictureParameterBufferH264 *pPicParameter =
> + (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
> +
> + if (!pSeqParameter->seq_fields.bits.seq_scaling_matrix_present_flag
> +&& !pPicParameter->pic_fields.bits.pic_scaling_matrix_present_flag) {
> + qm_4x4_intra = qm_4x4_inter = qm_8x8_intra = qm_8x8_inter = qm_flat;
> + } else {
> + VAIQMatrixBufferH264 *qm;
> + assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
> + qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
> + qm_4x4_intra = (unsigned int *)qm->ScalingList4x4[0];
> + qm_4x4_inter = (unsigned int *)qm->ScalingList4x4[3];
> + qm_8x8_intra = (unsigned int *)qm->ScalingList8x8[0];
> + qm_8x8_inter = (unsigned int *)qm->ScalingList8x8[1];
> + }
> +
> + gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm_4x4_intra, 12, encoder_context);
> + gen9_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm_4x4_inter, 12, encoder_context);
> + gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm_8x8_intra, 16, encoder_context);
> + gen9_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm_8x8_inter, 16, encoder_context);
> }
>
> static void
> gen9_mfc_fqm_state(VADriverContextP ctx,
> int fqm_type,
> - unsigned int *fqm,
> + const uint32_t *fqm,
> int fqm_length,
> struct intel_encoder_context *encoder_context)
> {
> @@ -342,23 +377,51 @@ gen9_mfc_fqm_state(VADriverContextP ctx,
> }
>
> static void
> -gen9_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
> +gen9_mfc_avc_fill_fqm(uint8_t *qm, uint16_t *fqm, int len)
> +{
> + int i, j;
> + for (i = 0; i< len; i++)
> + for (j = 0; j< len; j++)
> + fqm[i * len + j] = (1<< 16) / qm[j * len + i];
> +}
> +
> +static void
> +gen9_mfc_avc_fqm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> - unsigned int qm[32] = {
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000,
> - 0x10001000, 0x10001000, 0x10001000, 0x10001000
> - };
> -
> - gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, encoder_context);
> - gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, encoder_context);
> - gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, encoder_context);
> - gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, encoder_context);
> + VAEncSequenceParameterBufferH264 *pSeqParameter =
> + (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
> + VAEncPictureParameterBufferH264 *pPicParameter =
> + (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
> +
> + if (!pSeqParameter->seq_fields.bits.seq_scaling_matrix_present_flag
> +&& !pPicParameter->pic_fields.bits.pic_scaling_matrix_present_flag) {
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm_flat, 24, encoder_context);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm_flat, 24, encoder_context);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm_flat, 32, encoder_context);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm_flat, 32, encoder_context);
> + } else {
> + int i;
> + uint32_t fqm[32];
> + VAIQMatrixBufferH264 *qm;
> + assert(encode_state->q_matrix&& encode_state->q_matrix->buffer);
> + qm = (VAIQMatrixBufferH264 *)encode_state->q_matrix->buffer;
> +
> + for (i = 0; i< 3; i++)
> + gen9_mfc_avc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * i, 4);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, fqm, 24, encoder_context);
> +
> + for (i = 3; i< 6; i++)
> + gen9_mfc_avc_fill_fqm(qm->ScalingList4x4[i], (uint16_t *)fqm + 16 * (i - 3), 4);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, fqm, 24, encoder_context);
> +
> + gen9_mfc_avc_fill_fqm(qm->ScalingList8x8[0], (uint16_t *)fqm, 8);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, fqm, 32, encoder_context);
> +
> + gen9_mfc_avc_fill_fqm(qm->ScalingList8x8[1], (uint16_t *)fqm, 8);
> + gen9_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, fqm, 32, encoder_context);
> + }
> }
>
> static void
> @@ -688,8 +751,8 @@ static void gen9_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
> gen9_mfc_pipe_buf_addr_state(ctx, encoder_context);
> gen9_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
> mfc_context->avc_img_state(ctx, encode_state, encoder_context);
> - mfc_context->avc_qm_state(ctx, encoder_context);
> - mfc_context->avc_fqm_state(ctx, encoder_context);
> + mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
> + mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
> gen9_mfc_avc_directmode_state(ctx, encoder_context);
> intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
> }
More information about the Libva
mailing list